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TECHNICAL MANUAL
LSI53C875/875E PCI to Ultra SCSI I/O Processor
Version 4.2 April 2003
(R)
DB14-000165-01
This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000165-01, Sixth Edition (April 2003) This document describes the LSI Logic LSI53C875/875E PCI to Ultra SCSI I/O Processor and will remain the official reference source for all revisions/releases of this product until rescinded by an update. To receive product literature, visit us at http://www.lsilogic.com. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright (c) 1998-2001/2003 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, TolerANT, SDMS, and SCRIPTS are registered trademarks or trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.
ii
Preface
This book is the primary reference and technical manual for the LSI Logic LSI53C875/875E PCI to Ultra SCSI I/O Processor. It contains a complete functional description for the LSI53C875/875E and includes complete physical and electrical specifications for the LSI53C875/875E.
Audience This technical manual is intended for system designers and programmers who are using this device to design a SCSI port for PCI-based personal computers, workstations, or embedded applications.
Organization This document has the following chapters and appendixes:
*
Chapter 1, General Description, includes general information about the LSI53C875 and other members of the LSI53C8XX family of PCI to SCSI I/O Processors. Chapter 2, Functional Description, describes the main functional areas of the chip in more detail, including the interfaces to the SCSI bus. Chapter 3, PCI Functional Description, describes the chip's connection to the PCI bus, including the PCI commands and configuration registers supported. Chapter 4, Signal Descriptions, contains the pin diagrams and definitions of each signal. Chapter 5, SCSI Operating Registers, describes each bit in the operating registers, organized by address.
*
*
* *
Preface
iii
* * * *
Chapter 6, Instruction Set of the I/O Processor, defines all of the SCSI SCRIPTS instructions that are supported by the LSI53C875. Chapter 7, Instruction Set of the I/O Processor, contains the electrical characteristics and AC timings for the chip. Appendix A, Register Summary, is a register summary. Appendix B, External Memory Interface Diagram Examples, contains several example interface drawings to connect the LSI53C875 to an external ROM.
Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3 Parallel Interface) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface
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Preface
LSI Logic World Wide Web Home Page www.lsilogic.com SCSI SCRIPTSTM Processors Programming Guide, Version 2.2, Order Number S14044.A PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344
Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix "0x" --for example, 0x32CF. Binary numbers are indicated by the prefix "0b" --for example, 0b0011.0010.1100.1111.
Revision Record
Revision 1.0 2.0 3.0 4.0 4.1 4.2
Date 6/95 3/96 9/96 2/98 3/01 4/03
Remarks Revision 1.0 Revision 2.0. Fast-20 changed to Ultra SCSI throughout. Revision 3.0. Minor copy changes throughout. Revision 4.0. Minor copy changes throughout Product names changed from SYM to LSI. Revision 4.2. Correct VDD-S in Table 4.3
Preface
v
vi
Preface
Contents
Chapter 1
General Description 1.1 Package and Feature Options 1.2 Benefits of Ultra SCSI 1.3 TolerANT(R) Technology 1.4 LSI53C875 Benefits Summary 1.4.1 SCSI Performance 1.4.2 PCI Performance 1.4.3 Integration 1.4.4 Ease of Use 1.4.5 Flexibility 1.4.6 Reliability 1.4.7 Testability Functional Description 2.1 SCSI Functional Description 2.1.1 SCSI Core 2.1.2 DMA Core 2.1.3 SCRIPTS Processor 2.1.4 Internal SCRIPTS RAM 2.1.5 SDMS Software: The Total SCSI Solution 2.2 Designing an Ultra SCSI System 2.2.1 Using the SCSI Clock Doubler 2.3 Prefetching SCRIPTS Instructions 2.3.1 Opcode Fetch Burst Capability 2.4 External Memory Interface 2.5 PCI Cache Mode 2.5.1 Load/Store Instructions 2.5.2 3.3 V/5 V PCI Interface 2.5.3 Additional Access to General Purpose Pins
1-4 1-4 1-5 1-6 1-6 1-7 1-7 1-7 1-8 1-9 1-9
Chapter 2
2-1 2-1 2-2 2-2 2-3 2-3 2-4 2-4 2-5 2-6 2-6 2-8 2-8 2-9 2-9
Contents
vii
2.6
2.5.4 JTAG Boundary Scan Testing 2.5.5 Big and Little Endian Support 2.5.6 Loopback Mode 2.5.7 Parity Options 2.5.8 DMA FIFO 2.5.9 SCSI Bus Interface 2.5.10 Select/Reselect During Selection/Reselection 2.5.11 Synchronous Operation 2.5.12 Ultra SCSI Synchronous Data Transfers 2.5.13 Interrupt Handling 2.5.14 Chained Block Moves Power Management 2.6.1 Power State D0 2.6.2 Power State D3
2-10 2-10 2-12 2-12 2-15 2-19 2-25 2-25 2-27 2-28 2-34 2-38 2-38 2-39
Chapter 3
PCI Functional Description 3.1 PCI Addressing 3.1.1 PCI Bus Commands and Functions Supported 3.2 PCI Cache Mode 3.2.1 Support for PCI Cache Line Size Register 3.2.2 Selection of Cache Line Size 3.2.3 Alignment 3.2.4 Memory Move Misalignment 3.2.5 Memory Write and Invalidate Command 3.2.6 Memory Read Line Command 3.2.7 Memory Read Multiple Command 3.3 Configuration Registers Signal Descriptions 4.1 MAD Bus Programming SCSI Operating Registers Instruction Set of the I/O Processor 6.1 SCSI SCRIPTS 6.1.1 Sample Operation
3-1 3-2 3-4 3-4 3-5 3-5 3-6 3-6 3-8 3-9 3-11
Chapter 4
4-22
Chapter 5 Chapter 6
6-1 6-3
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Contents
6.2
6.3
6.4
6.5
6.6
6.7
Block Move Instructions 6.2.1 First Dword 6.2.2 Second Dword I/O Instruction 6.3.1 First Dword 6.3.2 Second Dword Read/Write Instructions 6.4.1 First Dword 6.4.2 Second Dword 6.4.3 Read-Modify-Write Cycles 6.4.4 Move To/From SFBR Cycles Transfer Control Instructions 6.5.1 First Dword 6.5.2 Second Dword Memory Move Instructions 6.6.1 Read/Write System Memory from SCRIPTS 6.6.2 Second Dword 6.6.3 Third Dword Load and Store Instructions 6.7.1 First Dword 6.7.2 Second Dword
6-5 6-5 6-12 6-12 6-12 6-21 6-21 6-21 6-22 6-22 6-24 6-26 6-26 6-33 6-33 6-34 6-35 6-35 6-37 6-38 6-39
Chapter 7
Instruction Set of the I/O Processor 7.1 DC Characteristics 7.2 TolerANT Technology Electrical Characteristics 7.3 AC Characteristics 7.4 PCI and External Memory Interface Timing Diagrams 7.4.1 Target Timing 7.4.2 Initiator Timing 7.4.3 External Memory Timing 7.5 PCI and External Memory Interface Timing 7.6 SCSI Timing Diagrams 7.7 Package Drawings Register Summary External Memory Interface Diagram Examples
7-1 7-7 7-10 7-13 7-15 7-24 7-32 7-50 7-51 7-58
Appendix A Appendix B
Contents
ix
Index Customer Feedback Figures 1.1 1.2 2.1 2.2 2.3 2.4 2.5 2.6 4.1 4.2 4.3 4.4 4.5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 LSI53C875 External Memory Interface LSI53C875 Chip Block Diagram DMA FIFO Sections LSI53C875 Host Interface Data Paths Differential Wiring Diagram Regulated Termination Determining the Synchronous Transfer Rate Block Move and Chained Block Move Instructions LSI53C875 Pin Diagram LSI53C875J Pin Diagram LSI53C875N Pin Diagram LSI53C875JB Pin Diagram (Top View) LSI53C875 Functional Signal Grouping SCRIPTS Overview Block Move Instruction Register I/O Instruction Register Read/Write Instruction Register Transfer Control Instructions Memory Move Instruction Load and Store Instruction Format Rise and Fall Time Test Conditions SCSI Input Filtering Hysteresis of SCSI Receiver Input Current as a Function of Input Voltage Output Current as Function of Output Voltage Clock Waveforms Reset Input Interrupt Output PCI Configuration Register Read PCI Configuration Register Write Operating Register/SCRIPTS RAM Read 1-2 1-3 2-15 2-16 2-22 2-24 2-26 2-35 4-2 4-3 4-4 4-5 4-9 6-4 6-7 6-15 6-23 6-28 6-36 6-40 7-8 7-8 7-9 7-9 7-10 7-11 7-12 7-13 7-15 7-16 7-17
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Contents
7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 B.1 B.2 B.3 B.4
Operating Register/SCRIPTS RAM Write External Memory Read External Memory Write Opcode Fetch, Nonburst Burst Opcode Fetch Back-to-Back Read Back-to-Back Write Burst Read Burst Write Read Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access Write Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access Read Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access Write Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access Read Cycle, Slow Memory ( 64 Kbyte) Write Cycle, Slow Memory ( 64 Kbyte) Read Cycle, Normal/Fast Memory ( 64 Kbyte) Write Cycle, Normal/Fast Memory ( 64 Kbyte) Read Cycle, Slow Memory ( 64 Kbyte) Write Cycle, Slow Memory ( 64 Kbyte) Initiator Asynchronous Send Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive Initiator and Target Synchronous Transfer 169-Pin PBGA (GV) Mechanical Drawing 160-pin PQFP (P3) Mechanical Drawing 64 Kbyte Interface with 200 ns Memory 64 Kbyte Interface with 150 ns Memory 256 Kbyte Interface with 150 ns Memory 512 Kbyte Interface with 150 ns Memory
7-18 7-20 7-22 7-24 7-25 7-26 7-27 7-28 7-30 7-32 7-34 7-36 7-38 7-40 7-42 7-44 7-45 7-46 7-48 7-51 7-52 7-52 7-53 7-53 7-58 7-59 B-1 B-2 B-3 B-4
Contents
xi
Tables 2.1 2.2 2.3 2.4 2.5 3.1 3.2 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 5.1 5.2 5.3 5.4 5.5 6.1 6.2 External Memory Support Bits Used for Parity Control and Generation SCSI Parity Control SCSI Parity Errors and Interrupts Differential Mode PCI Bus Commands and Encoding Types PCI Configuration Register Map LSI53C875, LSI53C875J, LSI53C875E, and LSI53C875JE Power and Ground Signals LSI53C875N Power and Ground Signals LSI53C875JB and LSI53C875JBE Power and Ground Signals System Signals Address and Data Signals Interface Control Signals Arbitration Signals Error Reporting Signals SCSI SIgnals Additional Interface Signals External Memory Interface Signals JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB Only) Subsystem Data Configuration Table for the LSI53C875E (PCI Rev ID 0x26) Subsystem Data Configuration Table for the LSI53C875 (PCI Rev ID 0x04), Revision G Only External Memory Support LSI53C875 Register Map Examples of Synchronous Transfer Periods for SCSI-1 Transfer Rates Example Transfer Periods for Fast SCSI-2 and Ultra SCSI Transfer Rates Maximum Synchronous Offset SCSI Synchronous Data FIFO Word Count SCRIPTS Instructions Read/Write Instructions 2-7 2-13 2-14 2-15 2-20 3-3 3-12 4-7 4-7 4-8 4-10 4-11 4-12 4-13 4-14 4-15 4-18 4-21 4-22 4-23 4-23 4-24 5-2 5-16 5-17 5-18 5-28 6-2 6-24
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Contents
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8
7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28
Absolute Maximum Stress Ratings Operating Conditions SCSI Signals--SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ SCSI Signals--SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/ Input Signals--CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/ Capacitance Output Signals--MAC/_TESTOUT, REQ/ Output Signals--IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/, MOE/, MWE/ Output Signal--SERR/ Bidirectional Signals--AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Bidirectional Signals--GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4 Bidirectional Signals--MAD[7:0] Input Signals--TDI, TMS, TCK (LSI53C875J, LSI53C875JB, LSI53C875N Only) Output Signal--TDO (LSI53C875, LSI53C875JB, LSI53C875N Only) TolerANT Technology Electrical Characteristics Clock Timing Reset Input Interrupt Output LSI53C875 PCI and External Memory Interface Timing Initiator Asynchronous Send Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive SCSI-1 Transfers (SE, 5.0 Mbytes/s) SCSI-1 Transfers (Differential, 4.17 Mbytes/s) SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers), 50 MHz Clock Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock
7-2 7-2 7-3 7-3 7-3 7-4 7-4
7-4 7-4 7-5 7-5 7-6 7-6 7-6 7-7 7-11 7-12 7-13 7-50 7-51 7-52 7-52 7-53 7-54 7-54 7-55 7-55 7-56
Contents
xiii
7.29
A.1 A.2
Ultra SCSI Differential Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock Configuration Registers LSI53C875 Register Map
7-57 A-1 A-2
xiv
Contents
Chapter 1 General Description
Chapter 1 is divided into the following sections:
* * * *
Section 1.1, "Package and Feature Options" Section 1.2, "Benefits of Ultra SCSI" Section 1.3, "TolerANT(R) Technology" Section 1.4, "LSI53C875 Benefits Summary"
This manual combines information on the LSI53C875 and LSI53C875E, which are PCI to Ultra SCSI I/O Processors. The LSI53C875E is a minor modification of the existing LSI53C875 product. It has all the functionality of the LSI53C875 with the addition of features to enable it to comply with the Microsoft PC 97 Hardware Design Guide. Specifically, the LSI53C875E has a Power Management Support enhancement. Because there are only slight differences between them, the LSI53C875 and LSI53C875E are referred to as LSI53C875 throughout this technical manual. Only the new enhancements are referred to as LSI53C875E. This technical manual assumes the user is familiar with the current and proposed standards for SCSI and PCI. For additional background information on these topics, please refer to the list of reference materials provided in the Preface of this document. The LSI53C875 brings high-performance I/O solutions to host adapter, workstation, and general computer designs, making it easy to add SCSI to any PCI system. The LSI53C875 has a local memory bus for local storage of the device's BIOS ROM in Flash memory or standard EPROMs. Most versions of the LSI53C875 support big and little endian byte addressing to accommodate a variety of data configurations. The LSI53C875 supports programming of local Flash memory for updates to BIOS or SCRIPTSTM programs.
LSI53C875/875E PCI to Ultra SCSI I/O Processor
1-1
The LSI53C875 is a pin-for-pin replacement for the LSI53C825 PCI to SCSI I/O processor, with added support for the SCSI-3 Ultra standard as well as other new features. Some software enhancements are needed to take advantage of the features and Ultra SCSI transfer rates supported by the LSI53C875. The LSI53C875 performs Ultra SCSI transfers or fast 8- or 16- bit SCSI transfers in Single-Ended (SE) or differential mode, and improves performance by optimizing PCI bus utilization. A system diagram showing the connections of the LSI53C875 with an external ROM or Flash memory is pictured in Figure 1.1. Figure 1.1 LSI53C875 External Memory Interface
VPP VPP Translator (Optional) VPP
GPIO4 MWE/ MOE/ MCE/ MAD[7:0] PCI Bus MAS0/ LSI53C875 SCSI Bus MAS1/ HCT374 HCT374
ROM or Flash Memory D[7:0] A[7:0]
A[15:8]
HCT374 GPIO2_MAS2/ BIG_LIT (Optional)
A[19:16]
1-2
General Description
A block diagram of the LSI53C875 is pictured in Figure 1.2. Figure 1.2 LSI53C875 Chip Block Diagram
PCI
PCI Master and Slave Control Block External Memory
Memory Control
Data FIFO 536 Bytes
SCSI SCRIPTS Processor
Operating Registers
Configuration Registers
SCRIPTS RAM
Local Bus Memory
SCSI FIFO and SCSI Control Block
TolerANT Drivers and Receivers
SCSI Bus
The LSI53C875 integrates a high-performance SCSI core, a PCI bus master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet the flexibility requirements of SCSI-3 and Ultra SCSI standards. It is designed to implement multithreaded I/O algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. The LSI53C875 is fully supported by the LSI Logic Storage Device Management System (SDMSTM), a software package that supports the Advanced SCSI Protocol Interface (ASPI) and the ANSI Common Access Method (CAM). SDMS software provides BIOS and driver support for hard disk, tape, removable media products, and CD-ROM under the major PC operating systems.
1-3
1.1 Package and Feature Options
The LSI53C875 is available in three versions with different packaging and feature options. The LSI53C875 is packaged in a 160-pin Plastic Quad Flat Pack (PQFP). The LSI53C875J is identical to the LSI53C875 with additional pins that support JTAG boundary scan testing. The JTAG boundary scan signals replace the TESTIN, MAC/_TESTOUT, BIG_LIT/, and SDIRP1 pins. The LSI53C875N includes all of the signals in the LSI53C875, with the addition of the JTAG pins and four additional signals for extended parity checking and generation. It is packaged in a 208-pin PQFP. The LSI53C875JB is identical to the LSI53C875J, but is packaged in a 169-pin Ball Grid Array (BGA). The LSI53C875E, LSI53C875JE, and LSI53C875JBE have been upgraded to include the power management features.
1.2 Benefits of Ultra SCSI
Ultra SCSI is an extension of the SCSI-3 standard that expands the bandwidth of the SCSI bus and allows faster synchronous SCSI transfer rates. When enabled, Ultra SCSI performs 20 megatransfers during an I/O operation, resulting in approximately twice the synchronous transfer rates of fast SCSI-2. The LSI53C875 can perform 8-bit, Ultra SCSI synchronous transfers as fast as 20 Mbytes/s. This advantage is most noticeable in heavily loaded systems, or large block size requirements, such as video on-demand and image processing. An advantage of Ultra SCSI is that it significantly improves SCSI bandwidth while preserving existing hardware and software investments. The LSI53C875 is compatible with all existing LSI53C825 and LSI53C825A software; the only changes required are to enable the chip to perform synchronous negotiations for Ultra SCSI rates. The LSI53C875 can use the same board socket as an LSI53C825, with the addition of an 80 MHz SCLK or enabling the internal SCSI clock doubler to provide the correct frequency when transferring synchronous SCSI data at 50 nanosecond transfer rates. Some changes to existing cabling or system designs may be needed to maintain signal integrity at Ultra SCSI synchronous transfer rates. These design issues are discussed in Chapter 2, "Functional Description."
1-4
General Description
1.3 TolerANT(R) Technology
The LSI53C875 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators. Active negation is enabled by setting bit 7 in the SCSI Test Three (STEST3) register. TolerANT receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. TolerANT receivers filter the SCSI bus signals to eliminate unwanted transitions, without the long signal delay associated with RC-type input filters. This improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with SCSI operations. TolerANT technology input signal filtering is a built-in feature of the LSI53C875 and all LSI Logic fast SCSI devices. On the LSI53C875, the user may select a filtering period of 30 or 60 ns, with bit 1 in the SCSI Test Two (STEST2) register. The benefits of TolerANT technology include increased immunity to noise when the signal is going HIGH, better performance due to balanced duty cycles, and improved fast SCSI transfer rates. In addition, TolerANT SCSI devices do not cause glitches on the SCSI bus at power-up or power-down, so other devices on the bus are also protected from data corruption. TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute.
TolerANT(R) Technology
1-5
1.4 LSI53C875 Benefits Summary
The section provides an overview of the LSI53C875 features and benefits. It contains information on SCSI Performance, PCI Performance, Integration, Ease of Use, Flexibility, Reliability, and Testability.
1.4.1 SCSI Performance
To improve SCSI performance, the LSI53C875:
* * * * * * * * *
Includes 4 Kbyte internal RAM for SCRIPTS instruction storage. Performs wide, Ultra SCSI synchronous transfers as fast as 40 Mbytes/s. Increases SCSI synchronous offset from 8 to 16 levels. Supports variable block size and scatter/gather data transfers. Performs sustained memory-to-memory DMA transfers faster than 47 Mbytes/s (@ 33 MHz). Minimizes SCSI I/O start latency. Performs complex bus sequences without interrupts, including restore data pointers. Reduces interrupt service routine overhead through a unique interrupt status reporting method. Performs fast and wide SCSI bus transfers in SE and differential mode. - - 10 Mbytes/s asynchronous (20 Mbytes/s with Ultra SCSI). 20 Mbytes/s synchronous (40 Mbytes/s with Ultra SCSI).
* * * * *
Supports Load and Store SCRIPTS instructions to increase the performance of data transfers to and from chip registers. Supports target disconnect and later reconnect with no interrupt to the system processor. Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast I/O context switching. Supports expanded Register Move instructions to support additional arithmetic capability. Complies with PCI Bus Power Management Specification (LSI53C875E) Revision 1.0.
1-6
General Description
1.4.2 PCI Performance
To improve PCI performance, the LSI53C875:
* * * * * * * *
Complies with PCI 2.1 specification. Bursts 2, 4, 8, 16, 32, 64, or 128 Dwords across PCI bus. Supports 32-bit word data bursts with variable burst lengths. Prefetches up to 8 Dwords of SCRIPTS instructions. Bursts SCRIPTS opcode fetches across the PCI bus. Performs zero wait-state bus master data bursts faster than 110 Mbytes/s (@ 33 MHz). Supports PCI Cache Line Size register. Supports PCI Write and Invalidate, Read Line, and Read Multiple commands.
1.4.3 Integration
The following features ease integration of the LSI53C875 into a system:
* * * * *
3.3 V/5 V PCI interface. Full 32-bit PCI DMA bus master. Memory Move instructions allow use as a third-party PCI bus DMA controller. High-performance SCSI core. Integrated SCRIPTS processor.
1.4.4 Ease of Use
The following features of the LSI53C875 make the device user friendly:
* * * *
Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS storage. Direct PCI to SCSI connection. Reduced SCSI development effort. Easily adapted to the Advanced SCSI Protocol Interface (ASPI) or the ANSI Common Access Method (CAM), with SDMS software.
LSI53C875 Benefits Summary
1-7
* * * * * *
Compiler-compatible with existing LSI53C7XX and LSI53C8XX family SCRIPTS. Direct connection to PCI, and SCSI SE and differential buses. Development tools and sample SCSI SCRIPTS available. Maskable and pollable interrupts. Wide SCSI, A or P cable, and up to 16 devices are supported. Three programmable SCSI timers: Select/Reselect, Handshake-toHandshake, and General Purpose. The time-out period is programmable from 100 s to greater than 25.6 seconds. SDMS software for complete PC-based operating system support. Support for relative jumps. SCSI Selected As ID bits for responding with multiple IDs.
* * *
1.4.5 Flexibility
The following features increase the flexibility of the LSI53C875:
* * * * * * * * * * * * * *
High level programming interface (SCSI SCRIPTS). Programs local memory and bus Flash memory. Big/little endian support. Selectable 88 or 536 byte DMA FIFO for backward compatibility. Tailored SCSI sequences execute from main system RAM or internal SCRIPTS RAM. Flexible programming interface to tune I/O performance or to adapt to unique SCSI devices. Support for changes in the logical I/O interface definition. Low level access to all registers and all SCSI bus signals. Fetch, Master, and Memory Access control pins. Separate SCSI and system clocks. SCSI clock doubler bits enable Ultra SCSI transfer rates with a 40 MHz SCSI clock. Selectable IRQ pin disable bit. 32 additional scratch pad registers. Ability to route system clock to SCSI clock.
1-8
General Description
1.4.6 Reliability
The following features enhance the reliability of the LSI53C875:
* * * * * * * * *
2 kV ESD protection on SCSI signals. Typical 300 mV SCSI bus hysteresis. Protection against bus reflections due to impedance mismatches. Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certification). Latch-up protection greater than 150 mA. Voltage feed-through protection (minimum leakage current through SCSI pads). A high proportion (> 25%) of pins are power and ground. Power and ground isolation of I/O pads and internal chip logic. TolerANT technology which provides: - - Active negation of SCSI Data, Parity, Request, and Acknowledge signals for improved fast SCSI transfer rates. Input signal filtering on SCSI receivers improves data integrity, even in noisy cabling environments.
* * *
JTAG Boundary scan support (LSI53C875J, LSI53C875JB, LSI53C875N only). Extended PCI parity checking and generation (LSI53C875N only). Extended SCSI parity checking.
1.4.7 Testability
The following features enhance the testability of the LSI53C875:
* * * * * *
Access to all SCSI signals through programmed I/O. SCSI loopback diagnostics. SCSI bus signal continuity checking. Support for single step mode operation. Test mode (AND tree) to check pin continuity to the board (most package options). JTAG Boundary scan support (LSI53C875J, LSI53C875JB, LSI53C875N only).
LSI53C875 Benefits Summary
1-9
1-10
General Description
Chapter 2 Functional Description
Chapter 2 is divided into the following sections:
* * * * * *
Section 2.1, "SCSI Functional Description" Section 2.2, "Designing an Ultra SCSI System" Section 2.3, "Prefetching SCRIPTS Instructions" Section 2.4, "External Memory Interface" Section 2.5, "PCI Cache Mode" Section 2.6, "Power Management"
2.1 SCSI Functional Description
The LSI53C875 is composed of three functional blocks: the SCSI Core, the DMA Core, and the SCRIPTS Processor. The LSI53C875 is fully supported by SDMS software, a complete software package that supports the LSI Logic product line of SCSI processors and controllers. The PCI Bus Power Management support (LSI53C875E) is discussed Section 2.6, "Power Management."
2.1.1 SCSI Core
The SCSI core supports the 8-bit or 16-bit data bus. It supports Ultra SCSI synchronous transfer rates up to 40 Mbytes/s, SCSI synchronous transfer rates up to 20 Mbytes/s, and asynchronous transfer rates up to 10 Mbytes/s on a 16-bit wide SCSI bus. The SCSI core can be programmed with SCSI SCRIPTS, making it easy to "fine tune" the system for specific mass storage devices or SCSI-3 requirements.
LSI53C875/875E PCI to Ultra SCSI I/O Processor
2-1
The SCSI core offers low level register access or a high level control interface. Like first generation SCSI devices, the LSI53C875 SCSI core can be accessed as a register oriented device. The ability to sample and/or assert any signal on the SCSI bus can be used in error recovery and diagnostic procedures. In support of loopback diagnostics, the SCSI core may perform a self-selection and operate as both an initiator and a target. The LSI53C875 SCSI core is controlled by the integrated SCRIPTS processor through a high level logical interface. Commands controlling the SCSI core are fetched out of the main host memory or local memory. These commands instruct the SCSI core to Select, Reselect, Disconnect, Wait for a Disconnect, Transfer Information, Change Bus Phases and, in general, implement all aspects of the SCSI protocol. The SCRIPTS processor is a special high speed processor optimized for SCSI protocol.
2.1.2 DMA Core
The DMA core is a bus master DMA device that attaches directly to the industry standard PCI Bus. The DMA core is tightly coupled to the SCSI core through the SCRIPTS processor, which supports uninterrupted scatter/gather memory operations. The LSI53C875 supports 32-bit memory and automatically supports misaligned DMA transfers. A 536-byte FIFO allows the LSI53C875 to support 2, 4, 8, 16, 32, 64, or 128 longword bursts across the PCI bus interface.
2.1.3 SCRIPTS Processor
The SCSI SCRIPTS processor allows both DMA and SCSI commands to be fetched from host memory or internal SCRIPTS RAM. Algorithms written in SCSI SCRIPTS control the actions of the SCSI and DMA cores and are executed from 32-bit system RAM. The SCRIPTS processor executes complex SCSI bus sequences independently of the host CPU. The SCRIPTS processor can begin a SCSI I/O operation in approximately 500 ns. This compares with 2-8 ms required for traditional intelligent host adapters. Algorithms may be designed to tune SCSI bus performance, to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the SCSI-2
2-2
Functional Description
or SCSI-3 logical bus definitions without sacrificing I/O performance. SCSI SCRIPTS are hardware independent, so they can be used interchangeably on any host or CPU system bus.
2.1.4 Internal SCRIPTS RAM
The LSI53C875 has 4 Kbyte (1024 x 32 bits) of internal, general purpose RAM. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS instructions or Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus. Other types of access to the RAM by the LSI53C875 use the PCI bus, as if they were external accesses. The MAD5 pin enables the 4 Kbyte internal RAM. To disable the internal RAM, connect a 4.7 k resistor between the MAD5 pin and VSS. The RAM can be relocated by the PCI system BIOS anywhere in 32-bit address space. The RAM Base Address register in PCI configuration space contains the base address of the internal RAM. This register is similar to the ROM Base Address register in PCI configuration space. To simplify loading of SCRIPTS instructions, the base address of the RAM will appear in the Scratch Register B (SCRATCHB) register when bit 3 of the Chip Test Two (CTEST2) register is set. The RAM is byte accessible from the PCI bus and is visible to any bus mastering device on the bus. External accesses to the RAM (by the CPU) follow the same timing sequence as a standard slave register access, except that the target wait-states required drop from 5 to 3. A complete set of development tools is available for writing custom drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS instructions supported by the LSI53C875, see Chapter 6, "Instruction Set of the I/O Processor."
2.1.5 SDMS Software: The Total SCSI Solution
For users who do not need to develop custom drivers, LSI Logic provides a total SCSI solution in PC environments with the SDMS. SDMS software provides BIOS driver support for hard disk, tape, and removable media peripherals for the major PC-based operating systems.
SCSI Functional Description
2-3
SDMS software includes a SCSI BIOS to manage all SCSI functions related to the device. It also provides a series of SCSI device drivers that support most major operating systems. SDMS software supports a multithreaded I/O application programming interface (API) for user developed SCSI applications. SDMS software supports both the ASPI and CAM SCSI software specifications.
2.2 Designing an Ultra SCSI System
Migrating an existing SE SCSI design from SCSI-2 to Ultra SCSI requires minor software modifications as well as consideration for some hardware design guidelines. Since Ultra SCSI is based on existing SCSI standards, it can use existing software programs as long as the software is able to negotiate for Ultra SCSI synchronous transfer rates. In the area of hardware, the primary area of concern in SE systems is to maintain signal integrity at high data transfer rates. To assure reliable operation at Ultra SCSI transfer speeds, follow the system design parameters recommended in the SCSI-3 Ultra Parallel Interface standard. Chapter 7, "Instruction Set of the I/O Processor," contains Ultra SCSI timing information. In addition to the guidelines in the draft standard, make the following software and hardware adjustments to accommodate Ultra SCSI transfers:
* * *
Set the Ultra Enable bit to enable Ultra SCSI transfers. Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3) register whenever the Ultra Enable bit is set. Do not extend the SREQ/SACK filtering period with SCSI Test Two (STEST2), bit 1.
2.2.1 Using the SCSI Clock Doubler
The LSI53C875 can double the frequency of a 40-50 MHz SCSI clock, allowing the system to perform Ultra SCSI transfers in systems that do not have 80 MHz clock input. This option is user selectable with bit settings in the SCSI Test One (STEST1), SCSI Test Three (STEST3), and SCSI Control Three (SCNTL3) registers. At power-on or reset, the doubler is disabled and powered down. Follow these steps to use the clock doubler:
2-4
Functional Description
Step 1. Set the SCLK Doubler Enable bit (SCSI Test One (STEST1), bit 3). Step 2. Wait 20 s. Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test Three (STEST3), bit 5). Step 4. Set the clock conversion factor using the SCF and CCF fields in the SCSI Control Three (SCNTL3) register. Step 5. Set the SCLK Doubler Select bit (SCSI Test One (STEST1), bit 2). Step 6. Clear the Halt SCSI Clock bit.
2.3 Prefetching SCRIPTS Instructions
When enabled by setting the Prefetch Enable bit in the DMA Control (DCNTL) register, the prefetch logic in the LSI53C875 fetches 8 Dwords of instructions. The prefetch logic automatically determines the maximum burst size that it can perform, based on the burst length as determined by the values in the DMA Mode (DMODE) register. If the unit cannot perform bursts of at least four Dwords, it disables itself. While the LSI53C875 is prefetching SCRIPTS instructions, the PCI Cache Line Size register value does not have any effect and the Read Line, Read Multiple, and Write and Invalidate commands are not used. The LSI53C875 may flush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. When one of these conditions apply, the contents of the prefetch unit are automatically flushed.
*
On every Memory Move instruction. The Memory Move instruction is often used to place modified code directly into memory. To make sure that the chip executes all recent modifications, the prefetch unit flushes its contents and loads the modified code every time an instruction is issued. To avoid inadvertently flushing the prefetch unit contents, use the No Flush option for all Memory Move operations that do not modify code within the next 8 Dwords. For more information on this instruction, refer to Chapter 6, "Instruction Set of the I/O Processor."
Prefetching SCRIPTS Instructions
2-5
*
On every Store instruction. The Store instruction may also be used to place modified code directly into memory. To avoid inadvertently flushing the prefetch unit contents use the No Flush option for all Store operations that do not modify code within the next 8 Dwords. On every write to the DMA SCRIPTS Pointer (DSP). On all Transfer Control instructions when the transfer conditions are met. This is necessary because the next instruction to execute is not the sequential next instruction in the prefetch unit. When the Prefetch Flush bit (DMA Control (DCNTL), bit 6) is set. The unit flushes whenever this bit is set. The bit is self-clearing.
* *
*
2.3.1 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit in the DMA Mode (DMODE) register (0x38) causes the LSI53C875 to burst in the first two longwords of all instruction fetches. If the instruction is a Memory-to-Memory Move, the third longword is accessed in a separate ownership. If the instruction is an indirect type, the additional longword is accessed in a subsequent bus ownership. If the instruction is a Table Indirect Block Move, the chip uses two accesses to obtain the four longwords required, in two bursts of two longwords each. Note: This feature is only useful if prefetching is disabled.
2.4 External Memory Interface
The LSI53C875 supports up to one megabyte of external memory in binary increments from 16 Kbytes, to allow the use of expansion ROM for add-in PCI cards. The device also supports Flash ROM updates through the add-in interface and the GPIO4 pin (used to control VPP, the power supply for programming external memory). This interface is designed for low speed operations such as downloading instruction code from ROM. It is not intended for dynamic activities such as executing instructions. System requirements include the LSI53C875, two or three external 8-bit address holding registers (HCT273 or HCT374), and the appropriate memory device. The 4.7 k pull-down resistors on the MAD bus require HC or HCT external components to be used. If in-system Flash ROM
2-6
Functional Description
updates are required, a 7406 (high voltage open collector inverter), an MTD4P05, and several passive components are also needed. The memory size and speed is determined by pull-down resistors on the 8-bit bidirectional memory bus at power-up. The LSI53C875 senses this bus shortly after the release of the Reset signal and configures the ROM Base Address register and the memory cycle state machines for the appropriate conditions. The external memory interface works with a variety of ROM sizes and speeds. An example set of interface drawings is in Appendix B, "External Memory Interface Diagram Examples." The LSI53C875 supports a variety of sizes and speeds of expansion ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of pins MAD[3:1] allows the user to define how much external memory is available to the LSI53C875. Table 2.1 shows the memory space associated with the possible values of MAD[3:1]. The MAD[3:1] pins are fully defined in Chapter 4, "Signal Descriptions." Table 2.1
MAD[3:1] 000 001 010 011 100 101 110 111
External Memory Support
Available Memory Space 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 1024 Kbytes No external memory present
To use one of the configurations mentioned above in a host adapter board design, put 4.7 k pull-down resistors on the MAD pins corresponding to the available memory space. For example, to connect to a 32 Kbytes external ROM, use pull-downs on MAD[3] and MAD[2]. If the external memory interface is not used, then no external resistors are
External Memory Interface
2-7
necessary since there are internal pull-ups on the MAD bus. The internal pull-up resistors are disabled when external pull-down resistors are detected, to reduce current drain. The LSI53C875 allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in PCI configuration space. For more information on how this works, refer to the PCI specification or the Expansion ROM Base Address register description in Chapter 3, "PCI Functional Description." MAD[0] is the slow ROM pin. When pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. The external memory interface also supports updates to Flash memory. The 12 V power supply for Flash memory, VPP, is enabled and disabled with the GPIO4 pin and the GPIO4 control bit. For more information on the GPIO4 pin, refer to Chapter 4, "Signal Descriptions."
2.5 PCI Cache Mode
The LSI53C875 supports the PCI specification for an 8-bit Cache Line Size register located in PCI configuration space. The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. In conjunction with the Cache Line Size register, the PCI commands Read Line, Read Multiple, and Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands. For more information on PCI cache mode operations, refer to Chapter 3, "PCI Functional Description."
2.5.1 Load/Store Instructions
The LSI53C875 supports the Load and Store instruction type, which simplifies the movement of data between memory and the internal chip registers. It also enables the chip to transfer bytes to addresses relative to the Data Structure Address (DSA) register. For more information on the Load and Store instructions, refer to Chapter 6, "Instruction Set of the I/O Processor."
2-8
Functional Description
2.5.2 3.3 V/5 V PCI Interface
The LSI53C875 can attach directly to a 3.3 V or a 5 V PCI interface, due to separate VDD pins for the PCI bus drivers. This allows the devices to be used on the universal board recommended by the PCI Special Interest Group.
2.5.3 Additional Access to General Purpose Pins
The LSI53C875 can access the GPIO0 and GPIO1 general purpose pins through register bits in the PCI configuration space, instead of using the General Purpose Pin Control (GPCNTL) register in the operating register space to control these pins. In the LSI Logic SDMS software, the configuration bits control pins as the clock and data lines, respectively. To access the GPIO[1:0] pins through the configuration space, connect a 4.7 k resistor between the MAD[7] pin and VSS. MAD[7] contains an internal pull-up that is sensed shortly after chip reset. If the pin is sensed high, GPIO[1:0] access is disabled; if it is low, GPIO[1:0] access is enabled. Additionally, if GPIO[1:0] access has been enabled through the MAD[7] pin and if GPIO0 and/or GPIO1 are sensed low after chip reset, GPIO[1:0] access is disabled. If GPIO[1:0] access through configuration space is enabled, the GPIO0 and GPIO1 pins cannot be controlled from the General Purpose Pin Control (GPCNTL) and General Purpose (GPREG) registers, but are observable from the General Purpose (GPREG) register. When GPIO[1:0] access is enabled, the Serial Interface Control register at configuration addresses 0x34-0x35 controls the GPIO0 and GPIO1 pins. For more information on GPIO[1:0] access, refer to the Serial Interface Control register description in Chapter 3, "PCI Functional Description." For more information on the GPIO pins, see Chapter 4, "Signal Descriptions." This does not apply to the LSI53C875E. Note: The LSI Logic SDMS software controls the GPIO0 and GPIO1 pins using the General Purpose Pin Control (GPCNTL) and General Purpose (GPREG) registers. Therefore, if using SDMS software, do not connect a 4.7 k resistor between MAD[7] and Vss.
PCI Cache Mode
2-9
2.5.4 JTAG Boundary Scan Testing
The LSI53C875J/LSI53C875N/LSI53C875JB include support for JTAG boundary scan testing in accordance with the IEEE 1149.1 specification with one exception, which is discussed in this section. The device accepts all required boundary scan instructions, including the optional CLAMP, HIGH-Z, and IDCODE instructions. The LSI53C875J/LSI53C875N/LSI53C875JB use an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register. This device can handle a 10 MHz TCK frequency for TDO and TDI. Due to design constraints, the RST/ pin (system reset) always 3-states the SCSI pins when it is asserted. Boundary scan logic does not control this action, and this is not compliant with the specification. There are two solutions that resolve this issue: 1. Use the RST/ pin as a boundary scan compliance pin. When the pin is deasserted, the device is boundary scan compliant and when asserted, the device is noncompliant. To maintain compliance the RST/ pin must be driven high. 2. When RST/ is asserted during boundary scan testing the expected output on the SCSI pins must be a HIGH-Z condition, and not what is contained in the boundary scan data registers for the SCSI pin output cells. Because of package limitations, the LSI53C875J/LSI53C875JB replaces the TESTIN, MAC/_TESTOUT, BIG_LIT/, and SDIRP1 signals with the JTAG boundary scan signals. The LSI53C875N includes support for these signals in addition to the JTAG pins.
2.5.5 Big and Little Endian Support
The LSI53C875/LSI53C875N supports both big and little endian byte ordering through pin selection. The LSI53C875J/LSI53C875JB operate in little endian mode only (the BIG_LIT pin is replaced by one of the JTAG boundary scan signals). In big endian mode, the first byte of an aligned SCSI to PCI transfer is routed to lane three and succeeding transfers are routed to descending lanes. This mode of operation also applies to data transfers over the add-in ROM interface. The byte of data accessed at
2-10
Functional Description
location 0x0000 from memory is routed to lane three, and the data at location 0x0003 is routed to byte lane 0. In little endian mode, the first byte of an aligned SCSI to PCI transfer is routed to lane zero and succeeding transfers are routed to ascending lanes. This mode of operation also applies to the add-in ROM interface. The byte of data accessed at location 0x0000 from memory is routed to lane zero, and the data at location 0x0003 is routed to byte lane 3. The Big_Lit pin gives the LSI53C875 the flexibility of operating with either big or little endian byte orientation. Internally, in either mode, the actual byte lanes of the DMA FIFO and registers are not modified. The LSI53C875 supports slave accesses in big or little endian mode. When a Dword is accessed, no repositioning of the individual bytes is necessary since Dwords are addressed by the address of the least significant byte. SCRIPTS always uses Dwords in 32-bit systems, so compatibility is maintained between systems using different byte orientations. When less than a Dword is accessed, individual bytes must be repositioned. Internally, the LSI53C875 adjusts the byte control logic of the DMA FIFO and register decodes to access the appropriate byte lanes. The registers always appear on the same byte lane, but the address of the register is repositioned. Big/little endian mode selection has the most effect on individual byte access. Internally, the LSI53C875 adjusts the byte control logic of the DMA FIFO and register decodes to enable the appropriate byte lane. The registers always appear on the same byte lane, but the address of the register is repositioned. Data to be transferred between system memory and the SCSI bus always starts at address zero and continues through address `n' - there is no byte ordering in the chip. The first byte in from the SCSI bus goes to address 0, the second to address 1, etc. Going out onto the SCSI bus, address zero is the first byte out on the SCSI bus, address 1 is the second byte, etc. The only difference is that in a little endian system, address 0 is on byte lane 0, and in big endian mode address zero is on byte lane 3. Correct SCRIPTS are generated if the SCRIPTS compiler is run on a system that has the same byte ordering as the target system. Any SCRIPTS patching in memory must patch the instruction with the byte ordering that the SCRIPTS processor expects.
PCI Cache Mode
2-11
Software drivers for the LSI53C875 should access registers by their logical name (that is, SCNTL0) rather than by their address. The logical name should be equated to the register's big endian address in big endian mode (SCNTL0 = 0x03), and its little endian address in little endian mode (SCNTL0 = 0x00). This way, there is no change to the software when moving from one mode to the other; only the equate statement setting the operating modes needs to be changed. Addressing of registers from within a SCRIPTS instruction is independent of bus mode. Internally, the LSI53C875 always operates in little endian mode.
2.5.6 Loopback Mode
The LSI53C875 loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. When the Loopback Enable bit is set in the SCSI Test One (STEST1) register, the LSI53C875 allows control of all SCSI signals whether the chip is operating in initiator or target mode. For more information on this mode of operation refer to the SCSI SCRIPTS Processors Programming Guide.
2.5.7 Parity Options
The LSI53C875 implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the SCSI bus to test parity error recovery procedures. Table 2.2 defines the bits that are involved in parity control and observation. Table 2.3 describes the parity control function of the Enable Parity Checking and Assert SCSI Even Parity bits in the SCSI Control Zero (SCNTL0) register. Table 2.4 describes the options available when a parity error occurs. The LSI53C875N has four additional parity pins for checking incoming data on the PCI bus. These pins are assigned to each byte of the PCI address/data bus, and work in addition to the PAR (PCI parity) pin. In PCI master read or slave write operations, each byte of incoming data on the PCI bus is checked against its corresponding parity line, in addition to the normal parity checking against the PCI PAR signal. In PCI master write or slave read operations, parity is generated for each byte. This extra parity checking is always enabled for the LSI53C875N. The host system must support these pins. This feature is not register selectable. A parity error on any Byte Parity pin for PCI master read or
2-12
Functional Description
slave write operations causes a fatal DMA interrupt; SCRIPTS stops running. Mask this interrupt with the EBPE Interrupt Enable bit, bit 1 in the DMA Interrupt Enable (DIEN) register. These additional parity pins in no way affect the generation or checking of the PCI specified parity line. Table 2.2
BIt Name Assert SATN/ on Parity Errors Enable Parity Checking
Bits Used for Parity Control and Generation
Location SCSI Control Zero (SCNTL0), Bit 1 SCSI Control Zero (SCNTL0), Bit 3 Description When this bit is set, the LSI53C875 automatically asserts the SATN/ signal upon detection of a parity error. SATN/ is only asserted in initiator mode. Enables the LSI53C875 to check for parity errors. The LSI53C875 checks for odd parity. This bit also checks for parity errors on the four additional parity pins on the LSI53C875N. Determines the SCSI parity sense generated by the LSI53C875 to the SCSI bus. Causes the LSI53C875 not to halt operations when a parity error is detected in target mode. Determines whether the LSI53C875 generates an interrupt when it detects a SCSI parity error. This status bit is set whenever the LSI53C875 has detected a parity error on the SCSI bus. This status bit represents the active HIGH current state of the SCSI SDP0 parity signal. This bit represents the active HIGH current state of the SCSI SDP1 parity signal. These bits reflect the SCSI odd parity signal corresponding to the data latched into the SCSI Input Data Latch (SIDL) register.
Assert Even SCSI Parity SCSI Control One (SCNTL1), Bit 2 Disable Halt on SATN/ or a Parity Error (Target Mode Only) Enable Parity Error Interrupt Parity Error SCSI Control One (SCNTL1), Bit 5 SCSI Interrupt Enable Zero (SIEN0), Bit 0 SCSI Interrupt Status Zero (SIST0), Bit 0 SCSI Status Zero (SSTAT0), Bit 0 SCSI Status Two (SSTAT2), Bit 0 SCSI Status Two (SSTAT2), Bit 3 and SCSI Status One (SSTAT1), Bit 3 Chip Test Four (CTEST4), Bit 3
Status of SCSI Parity Signal SCSI SDP1 Signal Latched SCSI Parity
Master Parity Error Enable
Enables parity checking during master data phases.
PCI Cache Mode
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Table 2.2
BIt Name
Bits Used for Parity Control and Generation (Cont.)
Location Description Set when the LSI53C875 as a master detects that a target device has signaled a parity error during a data phase. By clearing this bit, a Master Data Parity Error will not cause IRQ/ to be asserted, but the status bit will be set in the DMA Status (DSTAT) register. By clearing this bit, an Extended Byte Parity Error will not cause IRQ/ to be asserted, but the status bit will be set in the DMA Status (DSTAT) register.
Master Data Parity Error DMA Status (DSTAT), Bit 6 Master Data Parity Error Interrupt Enable Extended Byte Parity Error Interrupt Enable (LSI53C875N only) DMA Interrupt Enable (DIEN), Bit 6 DMA Interrupt Enable (DIEN), Bit 1
Table 2.3
EPC 0 0 1
SCSI Parity Control
AESP 0 1 0 Description Does not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. Does not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data. Checks for odd parity on SCSI data received. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. Checks for odd parity on SCSI data received. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data.
1
1
1. Key: EPC = Enable Parity Checking (bit 3, SCSI Control Zero (SCNTL0)). ASEP = Assert SCSI Even Parity (bit 2, SCSI Control One (SCNTL1)). 2. This table only applies when the Enable Parity Checking bit is set.
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Functional Description
Table 2.4
DPH 0 0 1 1
SCSI Parity Errors and Interrupts
PAR 0 1 0 1 Description Halts when a parity error occurs in target or initiator mode and does not generate an interrupt. Halts when a parity error occurs in target mode and generates an interrupt in the target or initiator mode. Does not halt in target mode when a parity error occurs until the end of the transfer. An interrupt is not generated. Does not halt in target mode when a parity error occurs until the end of the transfer. An interrupt is generated.
Key: DHP = Disable Halt on SATN/ or Parity Error (bit 5, SCSI Control One (SCNTL1). PAR = Parity Error (bit 0, SCSI Interrupt Enable One (SIEN1).
2.5.8 DMA FIFO
The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO is illustrated in Figure 2.1. To assure compatibility with older products in the LSI53C8XX family, the DMA FIFO size may be set to 88 bytes by setting the DMA FIFO Size bit, bit 5 in the Chip Test Five (CTEST5) register. Figure 2.1 DMA FIFO Sections
32 Bytes Wide
134 Transfers Deep
. . .
. . .
8 Bits Byte Lane 3
8 Bits Byte Lane 2
8 Bits Byte Lane 1
8 Bits Byte Lane 0
PCI Cache Mode
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2.5.8.1 Data Paths The data path through the LSI53C875 is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously. Figure 2.2 shows how data is moved to/from the SCSI bus in each of the different modes. Figure 2.2
Asynchronous SCSI Send PCI Interface
LSI53C875 Host Interface Data Paths
Asynchronous SCSI Receive PCI Interface Synchronous SCSI Send PCI Interface Synchronous SCSI Receive PCI Interface
DMA FIFO (32 Bits x 16)
DMA FIFO (32 Bits x 16)
DMA FIFO (32 Bits x 16)
DMA FIFO (32 Bits x 16)
SWIDE Register
SWIDE Register
SODL Register
SIDL Register
SODL Register
SCSI FIFO (8 or 16 Bits x 16)
SCSI Interface
SCSI Interface
SODR Register
SCSI Interface
SCSI Interface
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Functional Description
The following steps determine if any bytes remain in the data path when the chip halts an operation: Asynchronous SCSI Send - Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least significant bits of the DBC register from the 7-bit value of the DFIFO register. AND the result with 0x7F for a byte count between 0 and 88. If the DMA FIFO size is set to 536 bytes (bit 5 of the Chip Test Five (CTEST5) register), subtract the 10 least significant bits of the DMA Byte Counter (DBC) register from the 10-bit value of the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0] of the DMA FIFO (DFIFO) register. AND the result with 0x3FF for a byte count between 0 and 536. Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) registers to determine if any bytes are left in the SCSI Output Data Latch (SODL) register. If bit 5 is set in the SSTAT0 or SSTAT2 register, then the least significant byte or the most significant byte in the SODL register is full, respectively. Checking this bit also reveals bytes left in the SODL register from a Chained Move operation with an odd byte count. Synchronous SCSI Send - Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least significant bits of the DBC register from the 7-bit value of the DFIFO register. AND the result with 0x7F for a byte count between 0 and 88. If the DMA FIFO size is set to 536 bytes (bit 5 of the Chip Test Five (CTEST5) register), subtract the 10 least significant bits of the DMA Byte Counter (DBC) register from the 10-bit value of
PCI Cache Mode
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the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a byte count between 0 and 536. Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) registers to determine if any bytes are left in the SCSI Output Data Latch (SODL) register. If bit 5 is set in the SSTAT0 or SSTAT2 register, then the least significant byte or the most significant byte in the SODL register is full, respectively. Checking this bit also reveals bytes left in the SODL register from a Chained Move operation with an odd byte count. Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) registers to determine if any bytes are left in the SODR register. If bit 6 is set in the SSTAT0 or SSTAT2 register, then the least significant byte or the most significant byte in the SODR register is full, respectively. Asynchronous SCSI Receive - Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least significant bits of the DBC register from the 7-bit value of the DFIFO register. AND the result with 0x7F for a byte count between 0 and 88. If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip Test Five (CTEST5) register), subtract the 10 least significant bits of the DMA Byte Counter (DBC) register from the 10-bit value of the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a byte count between 0 and 536. Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) register to determine if any bytes are left in the SCSI Input Data Latch (SIDL) register. If bit 7 is set in the SSTAT0 or SSTAT2, then the least significant byte or the most significant byte is full, respectively.
2-18
Functional Description
Step 3. If any wide transfers have been performed using the Chained Move instruction, read the Wide SCSI Receive bit (SCSI Control Two (SCNTL2), bit 0) to determine whether a byte is left in the SCSI Wide Residue (SWIDE) register. Synchronous SCSI Receive - Step 1. If the DMA FIFO size is set to 88 bytes, subtract the seven least significant bits of the DMA Byte Counter (DBC) register from the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with 0x7F for a byte count between 0 and 88. If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip Test Five (CTEST5) register), subtract the 10 least significant bits of the DMA Byte Counter (DBC) register from the 10-bit value of the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a byte count between 0 and 536. Step 2. Read bits [7:4] of the SCSI Status One (SSTAT1) register and bit 4 of the SCSI Status Two (SSTAT2) register, the binary representation of the number of valid bytes in the SCSI FIFO, to determine if any bytes are left in the SCSI FIFO. Step 3. If any wide transfers have been performed using the Chained Move instruction, read the Wide SCSI Receive bit (SCSI Control Two (SCNTL2), bit 0) to determine whether a byte is left in the SCSI Wide Residue (SWIDE) register.
2.5.9 SCSI Bus Interface
The LSI53C875 supports both SE and differential operation. All SCSI signals are active low. The LSI53C875 contains the SE output drivers and can be connected directly to the SCSI bus. Each output is isolated from the power supply to ensure that a powered down LSI53C875 has no effect on an active SCSI bus (CMOS "voltage feed-through" phenomena). TolerANT technology provides signal filtering at the inputs of SREQ/ and SACK/ to increase immunity to signal reflections.
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2.5.9.1 Differential Mode In differential mode, the SDIR[15:0], SDIRP[1:0], IGS, TGS, RSTDIR, BSYDIR, and SELDIR signals control the direction of external differential pair transceivers. The LSI53C875 is placed in differential mode by setting the DIF bit, bit 5 of the SCSI Test Two (STEST2) register (0x4E). Setting this bit 3-states the BSY/, SEL/, and RST/ pads so they can be used as pure input pins. In addition to the standard SCSI lines, the following signals defined in Table 2.5 are used during differential operation by the LSI53C875:
Table 2.5
Signal
Differential Mode
Function Active HIGH signals used to enable the differential drivers as outputs for SCSI signals BSY/, SEL/, and RST/, respectively. Active HIGH signals used to control direction of the differential drivers for SCSI data and parity lines, respectively. Active HIGH signal used to control direction of the differential driver for initiator group signals ATN/ and ACK/. Active HIGH signal used to control direction of the differential drivers for target group signals MSG/, C/D/, I/O/, and REQ/. Input to the LSI53C875 used to detect the presence of a SE device on a differential system. If a logical zero is detected on this pin, then it is assumed that an SE device is on the bus and all SCSI outputs will be 3-stated to avoid damage to the transceiver.
BSYDIR, SELDIR, RSTDIR SDIR[15:0], SDIRP[1:0] IGS TGS DIFFSENS
See Figure 2.3 for an example differential wiring diagram, in which the LSI53C875 is connected to the Texas Instruments SN75976A differential transceiver. The recommended value of the pull-up resistor on the REQ/, ACK/, MSG/, C/D/, I/O/, ATN/, SD[7:0]/, and SDP0/ lines is 680 when the Active Negation portion of TolerANT technology is not enabled. When Active Negation is enabled, the recommended resistor value on the REQ/, ACK/, SD[7:0]/, and SDP0/ signals is 1.5 k. The electrical characteristics of these pins change when Active Negation is enabled, permitting a higher resistor value.
2-20
Functional Description
To interface the LSI53C875 to the SN75976A, connect the DIR pins, as well as IGS and TGS, of the LSI53C875 directly to the transceiver enables (nDE/RE/). These signals control the direction of the channels on the SN75976A. The SCSI bidirectional control and data pins (SD[7:0]/, SDP0/, REQ/, ACK/, MSG/, I_O/, C_D/, and ATN/) of the LSI53C875 connect to the bidirectional data pins (nA) of the SN75976A with a pull-up resistor. The pull-up value should be no lower than the transceiver IOL can tolerate, but not so high as to cause RC timing problems. The three remaining pins, SEL/, BSY/, and RST/ are connected to the SN75976A with a pull-down resistor. The pull-down resistors are required when the pins (nA) of the SN75976A are configured as inputs. When the data pins are inputs, the resistors provide a bias voltage to both the LSI53C875 pins (SEL/, BSY/, and RST/) and the SN75976A data pins. Because the SEL/, BSY/, and RST/ pins on the LSI53C875 are inputs only, this configuration allows for the SEL/, BSY/, and RST/ SCSI signals to be asserted on the SCSI bus. The differential pairs on the SCSI bus are reversed when connected to the SN75976A, due to the active low nature of the SCSI bus. Note: The SN75976A differential transceiver must be used to achieve Ultra SCSI transfer rates.
8-Bit/16-Bit SCSI and the Differential Interface - In an 8-bit SCSI bus, the SD[15:8] pins on the LSI53C875 should be pulled up with a 1.5 k resistor or terminated like the rest of the SCSI bus lines. This is very important, as errors may occur during reselection if these lines are left floating. In the LSI53C875J and LSI53C875JB, the SDIRP1 pin is replaced by the TCK JTAG signal. If the device is used in a wide differential system, use the SDIRP0 pin to control the direction of the differential transceiver for both the SP0 and SP1 signals. The SDIRP0 signal is capable of driving both direction inputs from a transceiver.
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Figure 2.3
Differential Wiring Diagram
DIFFSENS VDD Schottky Diode DIFFSENS (pin 21)
LSI53C8XX
SELDIR BSYDIR RSTDIR SEL/ BSY/ RST/ REQ/ ACK/ MSG/ C/D/ I/O/ ATN/ TGS IGS VDD SD[8:15]/ SDP1/ 1.5 K ATN/ VDD 1.5 K 1.5 K 1.5 K
1.5 K
SN75976A
CDE0 CDE1 CDE2 BSR CRE 1B+ -SEL (42) (41) 1B- +SEL 2B+ -BSY (34) 2B- +BSY (33) 3B+ -RST (38) 3B- +RST (37) 4B+ -REQ (46) 4B- +REQ (45) 5B+ -ACK (36) 5B- +ACK (35) 6B+ -MSG (40) 6B- +MSG (39) 7B+ -C/D (44) 7B- +C/D (43) -I/O (48) 8B+ +I/O (47) 8B- 9B+ -ATN (30) 9B- +ATN (29) SCSI Bus
SEL/ SELDIR BSY/
VDD
VDD RST/ 1.5 K
BSYDIR RSTDIR REQ/ ACK/ MSG/ C_D/ I_O/
1.5 K
1A 1DE/RE 2A 2DE/RE 3A 3DE/RE 4A 4DE/RE 5A 5DE/RE 6A 6DE/RE 7A 7DE/RE 8A 8DE/RE 9A 9DE/RE
SN75976A
DIFFSENS CDE0 CDE1 CDE2 BSR CRE 1A 1DE/RE 2A 2DE/RE 3A 3DE/RE 4A 4DE/RE 5A 5DE/RE 6A 6DE/RE 7A 7DE/RE 8A 8DE/RE 9A 9DE/RE 1B+ 1B- 2B+ 2B- 3B+ 3B- 4B+ 4B- 5B+ 5B- 6B+ 6B- 7B+ 7B- 8B+ 8B- 9B+ 9B- -DB0 +DB0 -DB1 +DB1 -DB2 +DB2 -DB3 +DB3 -DB4 +DB4 -DB5 +DB5 -DB6 +DB6 -DB7 +DB7 -DBP +DBP (4) (3) (6) (5) (8) (7) (10) (9) (12) (11) (14) (13) (16) (15) (18) (17) (20) (19)
VDD SDIRP0 SDIR7 SDIR6 SDIR5 SDIR4 SDIR3 SDIR2 SDIR1 SDIR0 SDP0/ SD7/ SD6/ SD5/ SD4/ SD3/ SD2/ SD1/ SD0/ DIFFSENS DIFFSENS 1.5 K SD0/ SDIR0 SD1/ SDIR1 SD2/ SDIR2 SD3/ SDIR3 SD4/ SDIR4 SD5/ SDIR5 SD6/ SDIR6 SD7/ SDIR7 SDP0/ SDIRP0
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Functional Description
2.5.9.2
Terminator Networks The terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. Terminators must be installed at the extreme ends of the SCSI chain, and only at the ends. No system should ever have more or less than two terminators installed and active. SCSI host adapters should provide a means of accommodating terminators. There should be a means of disabling termination. SE cables can use a 220 pull-up to the terminator power supply (Term Power) line and a 330 pull-down to ground. Because of the high-performance nature of the LSI53C875, regulated (or active) termination is recommended. Figure 2.4 shows a Unitrode active terminator. For additional information, refer to the SCSI-2 Specification. TolerANT technology active negation can be used with either termination network. Note: If the LSI53C875 is to be used in a design with only an 8-bit SCSI bus, all 16 data lines still must be terminated or pulled high. Active termination is required for Ultra SCSI synchronous transfers.
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Figure 2.4
Regulated Termination
UC5601QP
2.85 V
2 C1 C2
REG_OUT
TERML1 TERML2 TERML3 TERML4 TERML5 TERML6 TERML7 TERML8 TERML9
20 21 22 23 24 25 26 27 28
SD0 (J1.40) SD1 (J1.41) SD2 (J1.42) SD3 (J1.43) SD4 (J1.44) SD5 (J1.45) SD6 (J1.46) SD7 (J1.47) SDP (J1.48)
19 DISCONNECT
TERML10 TERML11 TERML12 TERML13 TERML14 TERML15 TERML16 TERML17 TERML18
3 4 5 6 7 8 9 10 11
ATN (J1.55) BSY (J1.57) ACK (J1.58) RST (J1.59) MSG (J1.60) SEL (J1.61) C/D (J1.62) REQ (J1.63) I/O (J1.64)
UC5603DP 14 C3 REG_OUT
6 DISCONNECT
TERML1 TERML2 TERML3 TERML4 TERML5 TERML6 TERML7 TERML8 TERML9
10 9 8 7 3 2 1 16 15
SD15 (J1.38) SD14 (J1.37) SD13 (J1.36) SD12 (J1.35) SD11 (J1.68) SD10 (J1.67) SD9 (J1.66) SD8 (J1.65) SDP1 (J1.39)
* * * *
Notes: C1 - 10 F SMT C2 - 0.1 F SMT C3 - 2.2 F SMT J1 - 68-pin, high density "P" connector
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Functional Description
2.5.10 Select/Reselect During Selection/Reselection
In multithreaded SCSI I/O environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. This situation may occur when a SCSI controller (operating in the initiator mode) tries to select a target and is reselected by another. The Select SCRIPTS instruction has an alternate address to which the SCRIPTS will jump when this situation occurs. The analogous situation for target devices is being selected while trying to perform a reselection. Once a change in operating mode occurs, the initiator SCRIPTS should start with a Set Initiator instruction or the target SCRIPTS should start with a Set Target instruction. The Selection and Reselection Enable bits (SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted so that the LSI53C875 may respond as an initiator or as a target. If only selection is enabled, the LSI53C875 cannot be reselected as an initiator. There are also status and interrupt bits in the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers, respectively, indicating that the LSI53C875 has been selected (bit 5) and reselected (bit 4).
2.5.11 Synchronous Operation
The LSI53C875 can transfer synchronous SCSI data in both the initiator and target modes. The SCSI Transfer (SXFER) register controls both the synchronous offset and the transfer period. It may be loaded by the CPU before SCRIPTS execution begins, from within SCRIPTS using a Table Indirect I/O instruction, or with a Read-Modify-Write instruction. The LSI53C875 can receive data from the SCSI bus at a synchronous transfer period as short as 50 ns, regardless of the transfer period used to send data. The LSI53C875 can receive data at one-fourth of the divided SCLK frequency. Depending on the SCLK frequency, the negotiated transfer period, and the synchronous clock divider, the LSI53C875 can send synchronous data at intervals as short as 50 ns for Ultra SCSI, 100 ns for fast SCSI, and 200 ns for SCSI-1.
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2.5.11.1 Determining the Data Transfer Rate Synchronous data transfer rates are controlled by bits in two different registers of the LSI53C875. Following is a brief description of the bits. Figure 2.5 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate. Figure 2.5 Determining the Synchronous Transfer Rate
SCF2 0 0 0 1 0 1 SCF1 0 1 1 0 0 0 SCF0 1 0 1 0 0 1 SCF Divisor 1 1.5 2 3 3 4 TP2 0 0 0 0 1 1 1 1 This point must not exceed 80 MHz SCF Divider SCLK Clock Doubler CCF Divider CCF2 0 0 0 1 0 1 CCF1 0 1 1 0 0 0 CCF0 1 0 1 0 0 1 Divisor 1 1.5 2 3 3 4 Asynchronous SCSI Logic TP1 0 0 1 1 0 0 1 1 Divide by 4 TP0 0 1 0 1 0 1 0 1 XFERP Divisor 4 5 6 7 8 9 10 11 Receive Clock Send Clock (to SCSI Bus)
Synchronous Divider
This point must not exceed 25 MHz
Example (8-bit SCSI bus): SCLK = 80 MHz, SCF = 1 (/ 1), XFERP = 4 (/ 4), CCF = 5 (/ 4) SCSI send rate = (SCLK / SCF) / XFERP = (80 / 1) / 4 = 20 Mbytes/s SCSI receive rate = (SCLK / SCF) / 4 = (80 / 1) / 4 = 20 Mbytes/s
2.5.11.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0]) The SCF[2:0] bits select the factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic. The output from this divider controls the rate at which data can be received; this rate must not exceed 80 MHz. The receive rate of synchronous SCSI data is one-fourth of the SCF divider output. For
2-26
Functional Description
example, if SCLK is 80 MHz and the SCF value is set to divide by two, then the maximum rate at which data can be received is 10 MHz (80/(2*4) = 10). 2.5.11.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0]) The CCF[2:0] bits select the factor by which the frequency of SCLK is divided before being presented to the asynchronous SCSI core logic. This divider must be set according to the input clock frequency in the table. 2.5.11.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0]) The TP[2:0] divider bits determine the SCSI synchronous transfer period when sending synchronous SCSI data in either initiator or target mode. This value further divides the output from the SCF divider. 2.5.11.5 Achieving Optimal SCSI Send Rates To achieve optimal synchronous SCSI send timings, the SCF divisor value should be set high, to divide the clock as much as possible before presenting the clock to the TP divider bits in the SCSI Transfer (SXFER) register. The TP[2:0] divider value should be as low as possible. For example, with an 80 MHz clock to achieve a 20 Mbytes/s Ultra SCSI send rate, the SCF bits can be set to divide by 1 (001) and the TP bits to divide by 4 (000). To set for a 10 Mbytes/s send rate for Fast SCSI2, the SCF bits can be set to divide by 2 (011) and the TP bits set to divide by 4 (000).
2.5.12 Ultra SCSI Synchronous Data Transfers
Ultra SCSI is an extension of current Fast SCSI-2 synchronous transfer specifications. It allows synchronous transfer periods to be negotiated down as low as 50 ns, which is half the 100 ns period allowed under Fast SCSI-2. This will allow a maximum transfer rate of 40 Mbytes/s on a 16-bit SCSI bus. The LSI53C875 requires an 80 MHz SCSI clock input to perform Ultra SCSI transfers. In addition, the following bit values affect the chip's ability to support Ultra SCSI synchronous transfer rates:
*
Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register bits [2:0] and Synchronous Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register bits [6:4]. These fields now support
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a value of 101 (binary), allowing the SCLK frequency to be divided down by 4. This allows systems using an 80 MHz clock or the internal clock doubler to operate at Fast SCSI-2 transfer rates as well as Ultra SCSI rates, if needed.
*
Ultra Mode Enable bit, SCSI Control Three (SCNTL3) register bit 7. Setting this bit enables Ultra SCSI synchronous transfers in systems that have an 80 MHz clock or use the internal SCSI clock doubler.
2.5.13 Interrupt Handling
The SCRIPTS processors in the LSI53C875 perform most functions independently of the host microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C875. 2.5.13.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts. Polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. This method is the fastest, but it wastes CPU time that could be used for other system tasks. The preferred method of detecting interrupts in most systems is hardware interrupts. In this case, the LSI53C875 asserts the Interrupt Request (IRQ/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. A hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.5.13.2 Registers The registers in the LSI53C875 that are used for detecting or defining interrupts are the Interrupt Status (ISTAT), SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), DMA Status (DSTAT), SCSI Interrupt Enable Zero (SIEN0), SCSI Interrupt Enable One (SIEN1), DMA Control (DCNTL), and DMA Interrupt Enable (DIEN). ISTAT - The ISTAT register is the only register that can be accessed as a slave during SCRIPTS operation. Therefore it is the register that is polled when polled interrupts are used. It is also the first register that should be read when the IRQ/ pin has been asserted in association with
2-28
Functional Description
a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first interrupt serviced. It must be written to one to be cleared. This interrupt must be cleared before servicing any other interrupts. If the SIP bit in the Interrupt Status (ISTAT) register is set, then a SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers should be read. If the DIP bit in the Interrupt Status (ISTAT) register is set, then a DMA-type interrupt has occurred and the DMA Status (DSTAT) register should be read. SCSI-type and DMA-type interrupts may occur simultaneously, so in some cases both SIP and DIP may be set. SIST0 and SIST1 - The SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers contain the SCSI-type interrupt bits. Reading these registers determines which condition or conditions caused the SCSI-type interrupt, and clears that SCSI interrupt condition. If the LSI53C875 is receiving data from the SCSI bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt. If the LSI53C875 is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could be left in the DMA FIFO. Because of this, the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be checked. If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three (CTEST3). The CSF bit is bit 1 in SCSI Test Three (STEST3). DSTAT - The DMA Status (DSTAT) register contains the DMA-type interrupt bits. Reading this register determines which condition or conditions caused the DMA-type interrupt, and clears that DMA interrupt condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate an interrupt under any circumstances and will not be cleared when read. DMA interrupts flush neither the DMA nor SCSI FIFOs before generating the interrupt, so the DFE bit in the DMA Status (DSTAT) register should be checked after any DMA interrupt.
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If the DFE bit is cleared, then the FIFOs must be cleared by setting the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by setting the FLF (Flush DMA FIFO) bit. SIEN0 and SIEN1 - The SCSI Interrupt Enable Zero (SIEN0) and SCSI Interrupt Enable One (SIEN1) registers are the interrupt enable registers for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1). DIEN - The DMA Interrupt Enable (DIEN) register is the interrupt enable register for DMA interrupts in DMA Status (DSTAT). DCNTL - When bit 1 in this register is set, the IRQ/ pin is not asserted when an interrupt condition occurs. The interrupt is not lost or ignored, but merely masked at the pin. Clearing this bit when an interrupt is pending immediately causes the IRQ/ pin to assert. As with any register other than ISTAT, this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution. 2.5.13.3 Fatal vs. Nonfatal Interrupts A fatal interrupt, as the name implies, always causes SCRIPTS to stop running. All nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. Interrupt masking is discussed Section 2.5.13.4, "Masking." All DMA interrupts (indicated by the DIP bit in ISTAT and one or more bits in DMA Status (DSTAT) being set) are fatal. Some SCSI interrupts (indicated by the SIP bit in the ISTAT and one or more bits in SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1) being set) are nonfatal. When the LSI53C875 is operating in Initiator mode, only the Function Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal. When operating in Target mode CMP, SEL, RSL, Target mode: SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP) bit in the SCSI Control One (SCNTL1) register to configure the chip's
2-30
Functional Description
behavior when the SATN/ interrupt is enabled during Target mode operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since SCRIPTS can continue when it occurs. The reason for nonfatal interrupts is to prevent SCRIPTS from stopping when an interrupt occurs that does not require service from the CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C875 has been selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire. These interrupts are not needed for events that occur during high-level SCRIPTS operation. 2.5.13.4 Masking Masking an interrupt means disabling or ignoring that interrupt. Interrupts can be masked by clearing bits in the SCSI Interrupt Enable Zero (SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts) registers or DMA Interrupt Enable (DIEN) (for DMA interrupts) register. How the chip responds to masked interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in Initiator or Target mode. If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the Interrupt Status (ISTAT) is not set, and the IRQ/ pin is not asserted. See Section 2.5.13.3, "Fatal vs. Nonfatal Interrupts," for a list of the nonfatal interrupts. If a fatal interrupt is masked and that condition occurs, then the SCRIPTS still stop, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0), or SCSI Interrupt Status One (SIST1) register is set, and the SIP or DIP bits in the Interrupt Status (ISTAT) is set, but the IRQ/ pin is not asserted. When the chip is initialized, enable all fatal interrupts if you are using hardware interrupts. If a fatal interrupt is disabled and that interrupt condition occurs, SCRIPTS halts and the system will never know it unless it times out and checks the ISTAT after a certain period of inactivity.
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If you are polling the ISTAT instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the SIP and DIP bits in the Interrupt Status (ISTAT) inform the system of interrupts, not the IRQ/ pin. Masking an interrupt after IRQ/ is asserted does not cause IRQ/ to be deasserted. 2.5.13.5 Stacked Interrupts The LSI53C875 will stack interrupts if they occur one after the other. If the SIP or DIP bits in the ISTAT register are set (first level), then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT) registers (second level). When two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT). When the first level of interrupts are cleared, all the interrupts that came in afterward move into the SIST0, SIST1, and DSTAT. After the first interrupt is cleared by reading the appropriate register, the IRQ/ pin is deasserted for a minimum of three CLKs; the stacked interrupts move into the SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), or DMA Status (DSTAT); and the IRQ/ pin is asserted once again. Since a masked nonfatal interrupt does not set the SIP or DIP bits, interrupt stacking does not occur. A masked, nonfatal interrupt still posts the interrupt in SIST0, but does not assert the IRQ/ pin. Since no interrupt is generated, future interrupts move right into the SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1) instead of being stacked behind another interrupt. When another condition occurs that generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. A related situation to interrupt stacking is when two interrupts occur simultaneously. Since stacking does not occur until the SIP or DIP bits are set, there is a small timing window in which multiple interrupts can occur but will not be stacked. These could be multiple SCSI interrupts (SIP set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple DMA interrupts (both SIP and DIP set).
2-32
Functional Description
As previously mentioned, DMA interrupts do not attempt to flush the FIFOs before generating the interrupt. It is important to set either the Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is because any future SCSI interrupts are not posted until the DMA FIFO is cleared of data. These `locked out' SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.5.13.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C875 attempts to halt in an orderly fashion.
*
If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault. Execution does not begin, but the DMA SCRIPTS Pointer (DSP) points to the next instruction since it is updated when the current instruction is fetched. If the DMA direction is a write to memory and a SCSI interrupt occurs, the LSI53C875 attempts to flush the DMA FIFO to memory before halting. Under any other circumstances only the current cycle is completed before halting, so the DFE bit in DSTAT should be checked to see if any data remains in the DMA FIFO. SCSI SREQ/SACK handshakes that have begun are completed before halting. The LSI53C875 attempts to clean up any outstanding synchronous offset before halting. In the case of Transfer Control Instructions, once instruction execution begins it continues to completion before halting. If the instruction is a JUMP/CALL WHEN/IF , the DMA SCRIPTS Pointer (DSP) is updated to the transfer address before halting. All other instructions may halt before completion.
*
* * * *
*
2.5.13.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C875. It can be repeated during polling or should be called when the IRQ/ pin is asserted during hardware interrupts.
PCI Cache Mode
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1. Read Interrupt Status (ISTAT). 2. If the INTF bit is set, it must be written to a one to clear this status. 3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt condition and get the SCSI interrupt status. The bits in the SIST0 and SIST1 tell which SCSI interrupts occurred and determine what action is required to service the interrupts. 4. If only the DIP bit is set, read the DMA Status (DSTAT) to clear the interrupt condition and get the DMA interrupt status. The bits in DSTAT tell which DMA interrupts occurred and determine what action is required to service the interrupts. 5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT) to clear the SCSI and DMA interrupt condition and get the interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT registers to clear interrupts, insert a 12 CLK delay between the consecutive reads to ensure that the interrupts clear properly. Both the SCSI and DMA interrupt conditions should be handled before leaving the interrupt service routine. It is recommended that the DMA interrupt be serviced before the SCSI interrupt, because a serious DMA interrupt condition could influence how the SCSI interrupt is acted upon. 6. When using polled interrupts, go back to Step 1 before leaving the interrupt service routine, in case any stacked interrupts moved in when the first interrupt was cleared. When using hardware interrupts, the IRQ/ pin is asserted again if there are any stacked interrupts. This should cause the system to re-enter the interrupt service routine.
2.5.14 Chained Block Moves
Since the LSI53C875 has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control Two (SCNTL2) register are used to facilitate these situations. The Chained Block Move instruction is illustrated in Figure 2.6.
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Functional Description
Figure 2.6
Block Move and Chained Block Move Instructions
SCSI Bus 0x00 0x04 0x08 00 04 08 0C 10 0x09 0x07 0x04 0x06 0x03 0x05
Host Memory 0x03 0x07 0x02 0x06 0x01 0x05
0x0B 0x0A 0x09
0x0F 0x0E 0x0D 0x0C 0x13 0x12 0x11 0x10
0x0B 0x0A 0x0D 0x0C
32 Bits
16 Bits
CHMOV 5, 3 when Data_Out Moves five bytes from address 0x03 in the host memory to the SCSI bus. Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the low-order byte of the SCSI Output Data Latch (SODL) register and is combined with the first byte of the following MOVE instruction. Move 5, 9 when Data_Out Moves five bytes from address 0x09 in the host memory to the SCSI bus. 2.5.14.1 Wide SCSI Send Bit The WSS bit is set whenever the SCSI controller is sending data (Data-Out for initiator or Data-In for target) and the controller detects a partial transfer at the end of a chained Block Move SCRIPTS instruction (this flag is not set if a normal Block Move instruction is used). Under this condition, the SCSI controller does not send the low-order byte of the last partial memory transfer across the SCSI bus. Instead, the low-order byte is temporarily stored in the lower byte of the SCSI Output Data Latch (SODL) register and the WSS flag is set. The hardware uses the WSS flag to determine what behavior must occur at the start of the next data
PCI Cache Mode
2-35
send transfer. When the WSS flag is set at the start of the next transfer, the first byte (the high-order byte) of the next data send transfer is "married" with the stored low-order byte in the SODL register; and the two bytes are sent out across the bus, regardless of the type of Block Move instruction (normal or chained). The flag is automatically cleared when the "married" word is sent. The flag can alternately be cleared through SCRIPTS or by the microprocessor. Also, the microprocessor or SCRIPTS can use this bit for error detection and recovery purposes. 2.5.14.2 Wide SCSI Receive Bit The WSR bit is set whenever the SCSI controller is receiving data (Data-In for initiator or Data-Out for target) and the controller detects a partial transfer at the end of a block move or chained block move SCRIPTS instruction. When WSR is set, the high-order byte of the last SCSI bus transfer is not transferred to memory. Instead, the byte is temporarily stored in the SCSI Wide Residue (SWIDE) register. The hardware uses the WSR bit to determine what behavior must occur at the start of the next data receive transfer. The bit is automatically cleared at the start of the next data receive transfer. The bit can alternatively be cleared by the microprocessor or through SCRIPTS. The bit can also be used by the microprocessor or SCRIPTS for error detection and recovery purposes. 2.5.14.3 SWIDE Register This register stores data for partial byte data transfers. For receive data, the SCSI Wide Residue (SWIDE) register holds the high-order byte of a partial SCSI transfer which has not yet been transferred to memory. This stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next Block Move instruction. 2.5.14.4 SODL Register For send data, the low-order byte of the SCSI Output Data Latch (SODL) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the SCSI bus. This stored data is usually "married" with the first byte of the next data send transfer, and both bytes are sent across the SCSI bus at the start of the next data send block move command.
2-36
Functional Description
2.5.14.5 Chained Block Move SCRIPTS Instruction A chained Block Move SCRIPTS instruction is primarily used to transfer consecutive data send or data receive blocks. Using the chained Block Move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. Behavior of the chained Block Move instruction varies slightly for sending and receiving data. For receive data (Data-In for initiator or Data-Out for target), a chained Block Move instruction indicates that if a partial transfer occurred at the end of the instruction, the WSR flag is set. The high-order byte of the last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register rather than transferred to memory. The contents of the SWIDE register should be the first byte transferred to memory at the start of the chained Block Move data stream. Since the byte count always represents data transfers to/from memory (as opposed to the SCSI bus), the byte transferred out of the SCSI Wide Residue (SWIDE) register is one of the bytes in the byte count. If the WSR bit is clear when a receive data chained Block Move instruction is executed, the data transfer occurs similar to that of the regular Block Move instruction. Whether the WSR bit is set or clear, when a normal block move instruction is executed, the contents of the SCSI Wide Residue (SWIDE) register are ignored and the transfer takes place normally. For "N" consecutive wide data receive Block Move instructions, the 2nd through the Nth Block Move instructions should be Chained Block Moves. For send data (Data-Out for initiator or Data-In for target), a chained Block Move instruction indicates that if a partial transfer terminates the chained Block Move instruction, the last low-order byte (the partial memory transfer) should be stored in the lower byte of the SCSI Output Data Latch (SODL) register and not sent across the SCSI bus. Without the chained block move instruction, the last low-order byte would be sent across the SCSI bus. The starting byte count represents data bytes transferred from memory but not to the SCSI bus when a partial transfer exists. For example, if the instruction is an Initiator chained Block Move Data Out of five bytes (and WSS is not previously set), five bytes are transferred out of memory to the SCSI controller, four bytes are transferred from the SCSI controller across the SCSI bus, and one byte is temporarily stored in the lower byte of the SCSI Output Data Latch (SODL) register waiting to be married with the first byte of the next Block Move instruction. Regardless of whether a chained Block Move or normal
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2-37
Block Move instruction is used, if the WSS bit is set at the start of a data send command, the first byte of the data send command is assumed to be the high-order byte and is "married" with the low-order byte stored in the lower byte of the SCSI Output Data Latch (SODL) register before the two bytes are sent across the SCSI bus. For "N" consecutive wide data send Block Move commands, the first through the (Nth - 1) Block Move instructions should be Chained Block Moves.
2.6 Power Management
The LSI53C875E complies with the PCI Bus Power Management Interface Specification, Revision 1.0. The PCI Function Power States D0, D1, D2, and D3 are defined in that specification. D0 and D3 are required by specification, and D1 and D2 are optional. D0 is the maximum powered state, and D3 is the minimum powered state. Power state D3 is further categorized as D3hot or D3cold. A function that is powered off is said to be in the D3cold power state. The power states for the SCSI function are independently controlled through two power state bits that are located in the PCI Configuration Space register 0x44. The bits are encoded as:
00b 01b 10b 11b D0 Reserved Reserved D3
Power states D1 and D2 are not discussed because they have not been implemented as a new feature. The Power states - D0 and D3 - are described below in conjunction with each SCSI function. Power state actions are separate for each function.
2.6.1 Power State D0
Power state D0 is the maximum power state and is the power-up default state for each function.
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Functional Description
2.6.2 Power State D3
Power state D3 is the minimum power state, which includes subsettings called D3hot and D3cold. The devices are considered to be in power state D3cold when power is removed from them. D3cold can transition to D0 by applying VCC and resetting the device. D3hot allows the device to transition to D0 using software. To obtain power reduction in D3hot, the SCSI clock and the SCSI clock doubler Phase Lock Loop (PLL) are disabled. Furthermore, the function's soft reset is continually asserted while in power state D3, which clears all pending interrupts and 3-states the SCSI bus. In addition, the function's PCI Command register is cleared.
Power Management
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2-40
Functional Description
Chapter 3 PCI Functional Description
This chapter is divided into the following sections:
* * *
Section 3.1, "PCI Addressing" Section 3.2, "PCI Cache Mode" Section 3.3, "Configuration Registers"
3.1 PCI Addressing
There are three types of PCI-defined address space:
* * *
Configuration space Memory space I/O space
The configuration space is a contiguous 256 x 8-bit set of addresses dedicated to each "slot" or "stub" on the bus. Decoding C_BE/[3:0] determines if a PCI cycle is intended to access configuration register space. The IDSEL bus signal is a "chip select" that allows access to the configuration register space only. A configuration read/write cycle without IDSEL is ignored. The eight lower order addresses select a specific 8-bit register. AD[10:8] are decoded as well, but they must be zero or the LSI53C875 does not respond. According to the PCI specification, AD[10:8] are reserved for multifunction devices. The host processor uses the PCI configuration space to initialize the LSI53C875. The lower 128 bytes of the LSI53C875 configuration space holds system parameters while the upper 128 bytes map into the LSI53C875 operating registers. For all PCI cycles except configuration cycles, the LSI53C875 registers are located on the 256-byte block boundary defined by the base
LSI53C875/875E PCI to Ultra SCSI I/O Processor
3-1
address assigned through the configured register. The LSI53C875 operating registers are available in both the upper and lower 128-byte portions of the 256-byte space selected. At initialization time, each PCI device is assigned a base address (in the case of the LSI53C875, the upper 24 bits of the address are selected) for memory and I/O accesses. On every access, the LSI53C875 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If the upper 24 bits match, the access is for the LSI53C875 and the low-order eight bits define the register to be accessed. A decode of C_BE/[3:0] determines which registers and what type of access is to be performed. The PCI specification defines memory space as a contiguous 32-bit memory address that is shared by all system resources, including the LSI53C875. Base Address One (Memory) determines which 256-byte memory area this device occupies. The PCI specification defines I/O space as a contiguous 32-bit I/O address that is shared by all system resources, including the LSI53C875. Base Address Zero (I/O) determines which 256-byte I/O area this device occupies.
3.1.1 PCI Bus Commands and Functions Supported
Bus commands indicate to the target the type of transaction the master is requesting. Bus commands are encoded on the C_BE/[3:0] lines during the address phase. PCI bus command encoding and types appear in Table 3.1.
3-2
PCI Functional Description
Table 3.1
PCI Bus Commands and Encoding Types
Supported as Master Supported as Slave No No Yes Yes N/A N/A Yes Yes N/A N/A No No Yes1 No Yes2 Yes3 No No Yes Yes N/A N/A Yes Yes N/A N/A Yes Yes No (defaults to 0110) No No (defaults to 0110) No (defaults to 0111)
C_BE[3:0] Command Type 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Special Interrupt Acknowledge Special Cycle I/O Read Cycle I/O Write Cycle Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
1. This operation is selectable by bit 2 in the DMA Mode (DMODE) operating register. 2. This operation is selectable by bit 3 in the DMA Mode (DMODE) operating register. 3. This operation is selectable by bit 0 in the Chip Test Three (CTEST3) operating register.
3.1.1.1 I/O Read Command The I/O Read command reads data from an agent mapped in I/O address space. All 32 address bits are decoded. 3.1.1.2 I/O Write Command The I/O Write command writes data to an agent when mapped in I/O address space. All 32 address bits are decoded.
PCI Addressing
3-3
3.1.1.3 Memory Read The Memory Read command reads data from an agent mapped in memory address space. All 32 address bits are decoded. 3.1.1.4 Memory Read Multiple The Memory Read command reads data from an agent mapped in memory address space. All 32 address bits are decoded. 3.1.1.5 Memory Read Line The Memory Read command reads data from an agent mapped in memory address space. All 32 address bits are decoded. 3.1.1.6 Memory Write The Memory Write command writes data to an agent when mapped in memory address space. All 32 address bits are decoded. 3.1.1.7 Memory Write and Invalidate The Memory Write command writes data to an agent when mapped in memory address space. All 32 address bits are decoded.
3.2 PCI Cache Mode
The LSI53C875 supports the PCI specification for an 8-bit Cache Line Size register located in the PCI configuration space. The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. In conjunction with the Cache Line Size register, the PCI commands Read Line, Read Multiple, and Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands.
3.2.1 Support for PCI Cache Line Size Register
The LSI53C875 supports the PCI specification for an 8-bit Cache Line Size register in PCI configuration space. It can sense and react to nonaligned addresses corresponding to cache line boundaries.
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PCI Functional Description
3.2.2 Selection of Cache Line Size
The cache logic selects a cache line size based on the values for the burst size in the DMA Mode (DMODE) register, bit 2 in the Chip Test Five (CTEST5) register, and the PCI Cache Line Size register. Note: The LSI53C875 does not automatically use the value in the PCI Cache Line Size register as the cache line size value. The chip scales the value of the Cache Line Size register down to the nearest binary burst size allowed by the chip (2, 4, 8, 16, 32, 64, or 128), compares this value to the burst size defined by the values of the DMA Mode (DMODE) register and bit 2 of the Chip Test Five (CTEST5) register, then selects the smallest as the value for the cache line size. The LSI53C875 uses this value for all burst data transfers.
3.2.3 Alignment
The LSI53C875 uses the calculated line size value to monitor the current address for alignment to the cache line size. When it is not aligned, the chip attempts to align to the cache boundary by using a "smart aligning" scheme. This means that it attempts to use the largest burst size possible that is less than the cache line size, to reach the cache boundary quickly with no overflow. This process is a stepping mechanism that steps up to the highest possible burst size based on the current address. The stepping process begins at a 4 Dword boundary. The LSI53C875 will first try to align to a 4 Dword boundary (0x00, 0x010, 0x020, etc.) by using single Dword transfers (no bursting). Once this boundary is reached the chip evaluates the current alignment to various burst sizes allowed, and selects the largest possible as the next burst size, while not exceeding the cache line size. The chip then issues this burst, and reevaluates the alignment to various burst sizes, again selecting the largest possible while not exceeding the cache line size, as the next burst size. This stepping process continues until the chip reaches the cache line size boundary or runs out of data. Once a cache line boundary is reached, the chip uses the cache line size as the burst size from then on, except in the case of multiples (explained below). The alignment process is finished at this point.
PCI Cache Mode
3-5
Example: Cache Line Size - 16, Current Address = 0x01 - The chip is not aligned to a 4 Dword cache boundary (the stepping threshold), so it issues four single Dword transfers (the first is a 3-byte transfer). At address 0x10, the chip is aligned to a 4 Dword boundary, but not aligned to any higher burst size boundaries that are less than the cache line size. So, the part issues a burst of 4. At this point, the address is 0x20, and the chip evaluates that it is aligned not only to a 4 Dword boundary, but also to an 8 Dword boundary. It selects the highest, 8, and bursts 8 Dwords. At this point, the address is 0x40, which is a cache line size boundary. Alignment stops, and the burst size from then on is switched to 16.
3.2.4 Memory Move Misalignment
The LSI53C875 does not operate in a cache alignment mode when a Memory Move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary. For example, if the read address is 0x21F and the write address is 0x42F, and the cache line size is 8, the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. The read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440. In this situation, the chip does not align to cache boundaries and operates as an LSI53C825.
3.2.5 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory Write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target. This command requires implementation of the PCI Cache Line Size register at address 0x0C in PCI configuration space. The LSI53C875 enables Memory Write and Invalidate cycles when bit 0 in the Chip Test Three (CTEST3) register (WRIE) and bit 4 in the PCI Command register are set. When the following conditions are met, Memory Write and Invalidate commands are issued: 1. The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register), WRIE bit (Write and Invalidate Enable, bit 0, Chip Test Three (CTEST3) register), and PCI configuration Command register, bit 4 are set.
3-6
PCI Functional Description
2. The Cache Line Size register contains a legal burst size (2, 4, 8, 16, 32, 64, or 128) value and that value must be less than or equal to the DMA Mode (DMODE) burst size. 3. The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst. 4. The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C875 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. Multiple Cache Line Transfers - The Write and Invalidate command can write multiple cache lines of data in a single bus ownership. The chip issues a burst transfer as soon as it reaches a cache line boundary. The size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size specified in the Revision 2.1 of the PCI specification. The logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being that determined from the DMA Mode (DMODE) burst size bits and Chip Test Five (CTEST5), bit 2. If multiple cache line size transfers are not desired, set the DMA Mode (DMODE) burst size to exactly the cache line size and the chip only issues single cache line transfers. After each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the DMA Mode (DMODE) burst size. The most likely scenario of this scheme is that the chip selects the DMA Mode (DMODE) burst size after alignment, and issues bursts of this size. The burst size is, in effect, throttled down toward the end of a long Memory Move or Block Move transfer until only the cache line size burst size is left. The chip finishes the transfer with this burst size. 3.2.5.1 Latency In accordance with the PCI specification, the latency timer is ignored when issuing a Write and Invalidate command such that when a latency time-out occurs, the LSI53C875 continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and finishes the
PCI Cache Mode
3-7
transfer at a later time using another bus ownership. If the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. PCI Target Retry - During a Write and Invalidate transfer, if the target device issues a retry (STOP with no TRDY, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip issues another Write and Invalidate command on the next ownership, in accordance with the PCI specification. PCI Target Disconnect - During a Write and Invalidate transfer, if the target device issues a disconnect the LSI53C875 relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip does not issue another Write and Invalidate command on the next ownership unless the address is aligned.
3.2.6 Memory Read Line Command
This command is identical to the Memory Read command, except that it additionally indicates that the master intends to fetch a complete cache line. This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading up to a cache line boundary rather than a single memory cycle. The Read Line function in the LSI53C875 takes advantage of the PCI 2.1 specification regarding issuing this command. The functionality of the Enable Read Line bit (bit 3 in DMA Mode (DMODE)) has been modified to more resemble the Write and Invalidate mode in terms of conditions that must be met before a Read Line command is issued. However, the Read Line option operates exactly like the previous LSI53C8XX chips when cache mode has been disabled by a CLSE bit reset or when certain conditions exist in the chip (explained below). The Read Line mode is enabled by setting bit 3 in the DMA Mode (DMODE) register. If cache mode is disabled, Read Line commands are issued on every read data transfer, except opcode fetches, as in previous LSI53C8XX chips. If cache mode is enabled, a Read Line command is issued on all read cycles, except opcode fetches, when the following conditions are met:
3-8
PCI Functional Description
1. The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE) register) bit are set. 2. The Cache Line Size register must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the DMA Mode (DMODE) burst size. 3. The number of bytes to be transferred at the time a cache boundary has been reached is equal to or greater than the DMA Mode (DMODE) burst size. 4. The chip is aligned to a cache line boundary. When these conditions are met, the chip issues a Read Line command instead of a Memory Read during all PCI read cycles. Otherwise, it issues a normal Memory Read command.
3.2.7 Memory Read Multiple Command
This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C875 supports PCI Read Multiple functionality and issues Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled. This mode is enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If cache mode is enabled, a Read Multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met: 1. The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode (DMODE) register) are set. 2. The Cache Line Size register contains a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the DMA Mode (DMODE) burst size. 3. The number of bytes to be transferred at the time a cache boundary is reached must be at least twice the full cache line size. 4. The chip is aligned to a cache line boundary. When these conditions are met, the chip issues a Read Multiple command instead of a Memory Read during all PCI read cycles.
PCI Cache Mode
3-9
Burst Size Selection - The Read Multiple command reads in multiple cache lines of data in a single bus ownership. The number of cache lines to be read is a multiple of the cache line size specified in Revision 2.1 of the PCI specification. The logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being determined from the DMA Mode (DMODE) burst size bits and Chip Test Five (CTEST5), bit 2. Read Multiple with Read Line Enabled - When both the Read Multiple and Read Line modes are enabled, the Read Line command is not issued if the above conditions are met. Instead, a Read Multiple command is issued, even though the conditions for Read Line are met. If the Read Multiple mode is enabled and the Read Line mode is disabled, Read Multiple commands are issued if the Read Multiple conditions are met. Unsupported PCI Commands - The LSI53C875 does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. It never generates these commands as a master.
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PCI Functional Description
3.3 Configuration Registers
The Configuration registers are accessible only by the system BIOS during PCI configuration cycles. The lower 128 bytes hold configuration data while the upper 128 bytes hold the LSI53C875 operating registers, which are described in Chapter 5, "SCSI Operating Registers." These registers are accessed by SCRIPTS or the host processor, if necessary. Note: The configuration register descriptions provide general information only, to indicate which PCI configuration addresses are supported in the LSI53C875. For detailed information, refer to the PCI Specification.
Table 3.2 shows the PCI configuration registers implemented by the LSI53C875/875E. All PCI-compliant devices, such as the LSI53C875, must support the Vendor ID, Device ID, Command, and Status registers. Support of other PCI-compliant registers is optional. In the LSI53C875, registers that are not supported are not writable and returns all zeros when read. Only those registers and bits that are currently supported by the LSI53C875 are described in this chapter. For more detailed information on PCI registers, please see the PCI Specification.
Configuration Registers
3-11
Table 3.2
31
PCI Configuration Register Map
16 15 Device ID Status Class Code Vendor ID Command Revision ID Latency Timer (I/O)1 Cache Line Size 0 0x00 0x04 0x08 0x0C 0x10 0x14 RAM3 0x18 0x1C 0x20 0x24 0x28 Subsystem Vendor ID (SSVID) Address4 Capabilities Pointer Reserved 0x2C 0x30 0x34 0x38 Interrupt Pin Next Item Pointer Interrupt Line Capability ID 0x3C 0x40 0x44
Not Supported
Header Type
Base Address Zero
Base Address One (Memory)2 Base Address Two (Memory) SCRIPTS Not Supported Not Supported Not Supported Reserved Subsystem ID (SSID) Expansion ROM Base Reserved
Max_Lat
Min_Gnt
Power Management Capabilities Data Bridge Support Extensions (PMCSR_BSE)
Power Management Control/Status
1. I/O Base is supported. 2. Memory Base is supported. 3. This register powers up enabled and can be disabled by pull-down resistors on the MAD5 pin. 4. If expansion memory is enabled through pull-down resistors on the MAD[7:0] bus. Note: Addresses 0x40-0x7F are not defined for the LSI53C875. Addresses 0x48-0x7F are not defined for the LSI53C875E. All unsupported registers are not writable and return all zeros when read. Reserved registers also return zeros when read.
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PCI Functional Description
Register: 0x00
Vendor ID Read Only
15 VID 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
VID
Vendor ID [15:0] This 16-bit register identifies the manufacturer of the device. The Vendor ID is 0x1000.
Register: 0x02
Device ID Read Only
15 DID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DID
Device ID [15:0] This 16-bit register identifies the particular device. The LSI53C875 Device ID is 0x000F.
Register: 0x04
Command Read/Write
15 R 0 0 0 0 0 0 0 9 8 SE 0 7 R 0 6 EPER 0 5 R 0 4 WIE 0 3 R 0 2 EBM 0 1 EMS 0 0 EIS 0
The Command register provides coarse control over a device's ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C875 is logically disconnected from the PCI bus for all accesses except configuration accesses. In the LSI53C875, bits 3, 5, 7, and 9 are not implemented. Bits 10 through 15 are reserved.
Configuration Registers
3-13
R
Reserved
[15:9]
SERR/ Enable 8 This bit enables the SERR/ driver. SERR/ is disabled when this bit is cleared. The default value of this bit is zero. This bit and bit 6 must be set to report address parity errors. R Reserved 7
Enable Parity Error Response 6 This bit allows the LSI53C875 to detect parity errors on the PCI bus and report these errors to the system. Only data parity checking is enabled. The LSI53C875 always generates parity for the PCI bus. R WIE Reserved 5
Write and Invalidate Mode 4 This bit allows the LSI53C875 to generate memory write and invalidate commands on the PCI bus. The WIE bit in the DMA Control (DCNTL) register must also be set for the device to generate Write and Invalidate commands. For more information on these conditions, refer to the section Section 3.2.5, "Memory Write and Invalidate Command." To enable Write and Invalidate Mode, set bit 0 in the Chip Test Three (CTEST3) register (operating register set). Reserved 3
R EBM
Enable Bus Mastering 2 This bit controls the ability of the LSI53C875 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C875 to behave as a bus master. The LSI53C875 must be a bus master in order to fetch SCRIPTS instructions and transfer data. Enable Memory Space 1 This bit controls the ability of the LSI53C875 to respond to Memory Space accesses. A value of zero disables the device response. A value of one allows the LSI53C875 to respond to Memory Space accesses at the address specified by Base Address One (Memory).
EMS
3-14
PCI Functional Description
EIS
Enable I/O Space 0 This bit controls the LSI53C875 response to I/O space accesses. A value of zero disables the device response. A value of one allows the LSI53C875 to respond to I/O space accesses at the address specified in Base Address Zero (I/O).
Register: 0x06
Status Read/Write
15 14 13 12 11 R 0 10 9 8 DPR 0 0 7 R 0 0 5 4 NC 1 0 0 3 R 0 0 0
DPE SSE RMA RTA 0 0 0 0
DT[1:0] 0 0
The Status register records status information for PCI bus related events. In the LSI53C875, bits 0 through 3 are reserved and bits 5, 6, 7, and 11 are not implemented by the LSI53C875. Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a one. For instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. DPE Detected Parity Error (from Slave) 15 This bit is set by the LSI53C875 whenever it detects a data parity error, even if parity error handling is disabled. Signaled System Error 14 This bit is set whenever a device asserts the SERR/ signal. Master Abort (from Master) 13 A master device should set this bit whenever its transaction (except for Special Cycle) is terminated with Master Abort. All master devices should implement this bit. Received Target Abort (from Master) A master device should set this bit whenever its transaction is terminated by target abort. All master devices should implement this bit. 12
SSE
RMA
RTA
Configuration Registers
3-15
R DT[1:0]
Reserved
11
DEVSEL/Timing [10:9] These bits encode the timing of DEVSEL/. These are encoded as
0b00 0b01 0b10 0b11 fast medium slow reserved
These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C875 supports a value of 0b01. DPR Data Parity Reported This bit is set when the following conditions are met: 8
* The bus agent asserted PERR/ itself or observed
PERR/ asserted.
* The agent setting this bit acted as the bus master for
the operation in which the error occurred.
* The Parity Error Response bit in the Command
register is set. R NC Reserved [7:5]
New Capabilities 4 This bit is set to indicate a list of extended capabilities such as PCI Power Management. This bit is read only. Reserved [3:0]
R
3-16
PCI Functional Description
Register: 0x08
Revision ID Read Only
7 RID LSI53C875E 0 LSI53C875 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0
RID
Revision ID [7:0] This register specifies device and revision identifiers. The value of the LSI53C875E is 0x26 and 0x0 for the LSI53C875.
Register: 0x09
Class Code Read Only
23 CC 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CC
Class Code [23:0] This 24-bit register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register level programming interface. The value of this register is 0x010000, which indicates a SCSI controller.
Configuration Registers
3-17
Register: 0x0C
Cache Line Size Read/Write
7 CLS 0 0 0 0 0 0 0 0 0
CLS
Cache Line Size [7:0] This register specifies the system cache line size in units of 32-bit words. Cache mode is enabled and disabled by the Cache Line Size Enable (CLSE) bit, bit 7 in the DMA Control (DCNTL) register. Setting this bit causes the LSI53C875 to align to cache line boundaries before allowing any bursting, except during Memory Moves in which the read and write addresses are not aligned to a burst size boundary. For more information on this register, see the section Section 3.2.1, "Support for PCI Cache Line Size Register."
Register: 0x0D
Latency Timer Read/Write
7 LT 0 0 0 0 0 0 0 0 0
LT
Latency Timer [7:0] The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The LSI53C875 supports this timer. All eight bits are writable, allowing latency values of 0-255 PCI clocks. Use the following equation to calculate an optimum latency value for the LSI53C875: Latency = 2 + (Burst Size x (typical wait states +1)) Values greater than optimum are also acceptable.
3-18
PCI Functional Description
Register: 0x0E
Header Type Read Only
7 HT 0 0 0 0 0 0 0 0 0
HT
Header Type [7:0] This register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions. The value of this register is 0x00.
Register: 0x10
Base Address Zero (I/O) Read/Write
31 BAR0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 0
BAR0
Base Address Register Zero (I/O) [31:0] This 32-bit register has bit zero hardwired to one. Bit 1 is reserved and must return a zero on all reads, and the other bits are used to map the device into I/O space.
Register: 0x14
Base Address One (Memory) Read/Write
31 BAR1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0
BAR1
Base Address Register One [31:0] This register has bit 0 hardwired to zero. For detailed information on the operation of this register, refer to the PCI Specification.
Configuration Registers
3-19
Register: 0x18
RAM Base Address Two (Memory) SCRIPTS RAM Read/Write
31 BAR2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0
BAR2
Base Address Register Two [31:0] This register holds the memory base address of the 4 Kbyte internal RAM. Read this register through the Scratch Register B (SCRATCHB) register in the operating register set when bit 3 of the Chip Test Two (CTEST2) register is set.
Register: 0x2C
Subsystem Vendor ID (SSVID) Read Only
15 SSVID LSI53C875E 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
LSI53C875 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSVID
Subsystem Vendor ID [15:0] This register supports subsystem identification, which has a default value of 0x0000 in the LSI53C875 and 0x1000 in the LSI53C875E (see Section 4.1, "MAD Bus Programming"). To write to this register, connect a 4.7 k resistor between the MAD[6] pin and Vss and leave the MAD[4] pin unconnected. The MAD[6] and MAD[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. In revisions before Revision G of the LSI53C875, the MAD[6] and MAD[4] pins do not support the SSID and SSVID configurations, and only values of 0x0000 can be found in the Subsystem Data register.
3-20
PCI Functional Description
Register: 0x2E
Subsystem ID (SSID) Read Only
15 SSID LSI53C875E 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
LSI53C875 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSID
Subsystem ID [15:0] This register supports subsystem identification, which has a default value of 0x0000 in the LSI53C875 and 0x1000 in the LSI53C875E (see Section 4.1, "MAD Bus Programming"). To write to this register, connect a 4.7 k resistor between the MAD[6] pin and Vss and leave the MAD[4] pin unconnected. The MAD[6] and MAD[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. In revisions before Revision G of the LSI53C875, the MAD[6] and MAD[4] pins do not support the SSID and SSVID configurations, and only values of 0x0000 can be found in the Subsystem Data register.
Register: 0x30
Expansion ROM Base Address Read/Write
31 ERBA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERBA
Expansion ROM Base Address [31:0] This four-byte register handles the base address and size information for expansion ROM. It functions exactly like the Base Address Zero (I/O) and Base Address One (Memory) registers, except that the encoding of the bits is different. The upper 21 bits correspond to the upper 21 bits of the expansion ROM base address.
Configuration Registers
3-21
The Expansion ROM Enable bit, bit 0, is the only bit defined in this register. This bit is used to control whether or not the device accepts accesses to its expansion ROM. When the bit is set, address decoding is enabled, and a device can be used with or without an expansion ROM depending on the system configuration. To access the external memory interface, also set the Memory Space bit in the Command register. The host system detects the size of the external memory by first writing the Expansion ROM Base Address register with all ones and then reading back the register. The LSI53C875 responds with zeros in all don't care locations. The ones in the remaining bits represent the binary version of the external memory size. For example, to indicate an external memory size of 32 Kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits.
Register: 0x34
Capabilities Pointer Read Only
7 CP 0 1 0 0 0 0 0 0 0
CP
Capabilities Pointer [7:0] This register provides an offset into the function's PCI Configuration Space for the location of the first item in the capabilities linked list. Only the LSI53C875E sets this register to 0x40. The capability pointer replaces the General Purpose Pin Control (GPCNTL) register in earlier revisions of the LSI53C875.
3-22
PCI Functional Description
Register: 0x3C
Interrupt Line Read/Write
7 IL 0 0 0 0 0 0 0 0 0
IL
Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it configures the system. The value in this register tells which input of the system interrupt controller(s) the device's interrupt pin is connected to. Values in this register are specified by system architecture.
Register: 0x3D
Interrupt Pin Read Only
7 IP 0 0 0 0 0 0 0 1 0
IP
Interrupt Pin [7:0] This register tells which interrupt pin the device uses. Its value is set to 0x01, for the INTA/ signal.
Configuration Registers
3-23
Register: 0x3E
Min_Gnt Read Only
7 MG 0 0 0 1 0 0 0 1 0
MG
Min_Gnt [7:0] This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 microseconds. The LSI53C875 sets this register to 0x11.
Register: 0x3F
Max_Lat Read Only
7 ML 0 1 0 0 0 0 0 0 0
ML
Max_Lat [7:0] This register is used to specify the desired settings for latency timer values. Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in this register is in units of 0.25 microseconds. Values of zero indicate that the device has no major requirements for the settings of latency timers. The LSI53C875 sets this register to 0x40.
3-24
PCI Functional Description
Register: 0x40
Capability ID Read Only
7 CID 0 0 0 0 0 0 0 1 0
CID
Cap_ID [7:0] This register indicates the type of data structure currently being used. It is set to 0x01, indicating the Power Management Data Structure. Only the LSI53C875E sets this register to 0x01.
Register: 0x41
Next Item Pointer Read Only
7 NIP 0 0 0 0 0 0 0 0 0
NIP
Next_Item_Ptr [7:0] Bits [7:0] contain the offset location of the next item in the controller capabilities list. The default value for this register is 0x00, indicating that power management is the last capability in the linked list of extended capabilities. This register applies to the LSI53C875E only.
Register: 0x42
Power Management Capabilities Read Only
15 PMES[4:0] 0 0 0 0 0 11 10 9 8 R 0 0 0 6 5 4 3 2 VER[2:0] 1 1 1 0
D2S D1S 0 0
DSI APS PMEC 0 0 0
This register applies to the LSI53C875E only and indicates the power management capabilities.
Configuration Registers
3-25
PMES
PME Support This field is always set to 00000b because the LSI53C875E does not provide a PME signal.
[15:11]
D2S
D2 Support 10 This device does not support the D2 power management state, and this bit is set to zero. D1 Support 9 This device does not support the D1 power management state, and this bit is set to zero. Reserved [8:6]
D1S
R DSI
Device Specific Initialization 5 This bit is set to 0 to indicate that the device requires no special initialization before the generic class device driver is able to use it. Auxiliary Power Source 4 Because the device does not provide a PME signal, this bit always returns a 0. This indicates that no auxiliary power source is required to support the PME signal in the D3cold power management state. PME Clock 3 This bit always returns a zero value because the devices do not provide a PME signal. Version [2:0] This field is set to 001b to indicate that the device complies with Revision 1.0 of the PCI Power Management Interface Specification.
APS
PMEC
VER
Register: 0x44
Power Management Control/Status Read/Write
15 14 13 12 DSLT 0 0 0 0 9 8 PEN 0 0 0 0 7 R 0 0 0 2 1 0
PST DSCL 0 0 0
PWS 0 0
This register applies to the LSI53C875E only and indicates the power management control and status descriptions.
3-26
PCI Functional Description
PST
PME Status 15 The device always returns a zero for this bit, indicating that PME signal generation is not supported from D3cold. Data Scale This device does not support the Data register. Therefore, this field is always set to 00b. Data Select This device does not support the Data register. Therefore, this field is always set to 0000b. [14:13]
DSCL
DSLT
[12:9]
PEN
PME Enable 8 This device always returns a zero for this bit to indicate that PME assertion is disabled. Reserved [7:2]
R PWS
Power State [1:0] This two bit field determines the current power state for the function and is used to set the function to a new power state. The definition of the field values are:
0b00 0b01 0b10 0b11 D0 Reserved Reserved D3 hot
Register: 0x46
Bridge Support Extensions (PMCSR_BSE) Read Only
7 BSE 0 0 0 0 0 0 0 0 0
BSE
Bridge Support Extensions [7:0] This register applies to the LSI53C875E only and can support PCI bridge specific functionality, if required. The default value always returns 0x00.
Configuration Registers
3-27
Register: 0x47
Data Read Only
7 DATA 0 0 0 0 0 0 0 0 0
DATA
Data [7:0] This register applies to the LSI53C875E only and provides an optional mechanism for the function to report state dependent operating data. The LSI53C875E returns 0x00 as the default value.
3-28
PCI Functional Description
Chapter 4 Signal Descriptions
This chapter presents the LSI53C875 pin configuration and signal definitions using tables and illustrations. Figure 4.1 through Figure 4.4 are the pin diagrams for all versions of the LSI53C875 and Figure 4.5 is the functional signal grouping. The pin definitions are presented in Table 4.1 through Table 4.12. The LSI53C875 is a pin-for-pin replacement for the LSI53C825.
LSI53C875/875E PCI to Ultra SCSI I/O Processor
4-1
Figure 4.1
LSI53C875 Pin Diagram
AD24 AD25 VSS AD26 AD27 VDD-I AD28 AD29 VSS AD30 AD31 VDD-C REQ/ GNT/ VSS-C CLK RST/ SERR/ BIG_LIT/ MCE/ MOE/ MWE/ VDD MAS0/ MAS1/ SDIR12 SDIR13 VSS SDIR14 SDIR15 SDIRP1 SDIR0 VDD SDIR1 SDIR2 SDIR3 SDIR4 VSS SDIR5 SDIR6
C_BE3/ IDSEL AD23 VSS AD22 AD21 AD20 VDD-I AD19 VSS AD18 AD17 AD16 VSS C_BE2/ FRAME/ IRDY/ VSS TRDY/ DEVSEL/ VDD-I STOP/ VSS PERR/ PAR/ C_BE1/ VSS AD15 AD14 AD13 VSS AD12 VDD-I AD11 AD10 AD9 VSS AD8 C_BE0/ AD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
LSI53C875 PCI to SCSI I/O Processor 160-Pin Quad Flat Pack (Top View)
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SDIR7 SDIRP0 VDD SD12/ SD13/ SD14/ VSS-S SD15/ SDP1/ SD0/ SD1/ VSS-S SD2/ SD3/ SD4/ SD5/ VSS-S SD6/ SD7/ SDP0/ SATN/ VSS-S SBSY/ SACK/ SRST/ SMSG/ SSEL/ VSS-S SC_D/ SREQ/ SI_O/ SD8/ VSS-S SD9/ SD10/ SD11/ VDD SDIR8 SDIR9 SDIR10
Note: The decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. Capacitor values between 0.01 and 0.1 F should provide adequate noise isolation. Because of the number of high current drivers on the LSI53C875, a multilayer PC board with power and ground planes is required.
4-2
AD6 VSS AD5 AD4 VDD-I AD3 AD2 VSS AD1 AD0 VDD-C IRQ/ GPIO0_FETCH/ GPIO1_MASTER/ VSS-C SCLK TESTIN MAC/_TESTOUT MAD7 MAD6 MAD5 MAD4 VDD MAD3 MAD2 MAD1 MAD0 GPIO2_MAS2/ VSS GPIO3 GPIO4 DIFFSENS TGS VDD IGS SELDIR RSTDIR BSYDIR VSS SDIR11
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Signal Descriptions
Figure 4.2
LSI53C875J Pin Diagram
AD24 AD25 VSS AD26 AD27 VDD-I AD28 AD29 VSS AD30 AD31 VDD-C REQ/ GNT/ VSS-C CLK RST/ SERR/ TDI MCE/ MOE/ MWE/ VDD MAS0/ MAS1/ SDIR12 SDIR13 VSS SDIR14 SDIR15 TCK SDIR0 VDD SDIR1 SDIR2 SDIR3 SDIR4 VSS SDIR5 SDIR6
C_BE3/ IDSEL AD23 VSS AD22 AD21 AD20 VDD-I AD19 VSS AD18 AD17 AD16 VSS C_BE2/ FRAME/ IRDY/ VSS TRDY/ DEVSEL/ VDD-I STOP/ VSS PERR/ PAR/ C_BE1/ VSS AD15 AD14 AD13 VSS AD12 VDD-I AD11 AD10 AD9 VSS AD8 C_BE0/ AD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
LSI53C875J (JTAG) PCI to SCSI I/O Processor 160-Pin Quad Flat Pack (Top View)
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SDIR7 SDIRP0 VDD SD12/ SD13/ SD14/ VSS-S SD15/ SDP1/ SD0/ SD1/ VSS-S SD2/ SD3/ SD4/ SD5/ VSS-S SD6/ SD7/ SDP0/ SATN/ VSS-S SBSY/ SACK/ SRST/ SMSG/ SSEL/ VSS-S SC_D/ SREQ/ SI_O/ SD8/ VSS-S SD9/ SD10/ SD11/ VDD SDIR8 SDIR9 SDIR10
Note: The decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. Capacitor values between 0.01 and 0.1 F should provide adequate noise isolation. Because of the number of high current drivers on the LSI53C875, a multilayer PC board with power and ground planes is required.
AD6 VSS AD5 AD4 VDD-I AD3 AD2 VSS AD1 AD0 VDD-C IRQ/ GPIO0_FETCH/ GPIO1_MASTER/ VSS-C SCLK TMS TDO MAD7 MAD6 MAD5 MAD4 VDD MAD3 MAD2 MAD1 MAD0 GPIO2_MAS2/ VSS GPIO3 GPIO4 DIFFSENS TGS VDD IGS SELDIR RSTDIR BSYDIR VSS SDIR11
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
4-3
Figure 4.3
LSI53C875N Pin Diagram
NC NC NC NC AD24 AD25 VSS AD26 AD27 VDD-I AD28 AD29 VSS AD30 AD31 BYTEPAR3 VDD-C REQ/ GNT/ VSS-C CLK RST/ SERR/ TDI BIG_LIT/ MCE/ MOE/ MWE/ VDD MAS0/ MAS1 SDIR12 SDIR13 VSS SDIR14 SDIR15 TCK SDIRP1 SDIR0 VDD SDIR1 SDIR2 SDIR3 SDIR4 VSS SDIR5 SDIR6 NC NC NC NC NC
Note: The decoupling capacitor arrangement shown in Figures 4.1 and 4.2 is recommended to maximize the benefits of the internal split ground system. Capacitor values between 0.01 and 0.1 F should provide adequate noise isolation. Because of the number of high current drivers on the LSI53C875, a multilayer PC board with power and ground planes is required.
4-4
NC NC NC NC NC AD6 VSS AD5 AD4 VDD-I AD3 AD2 VSS AD1 AD0 VDD-C IRQ/ GPIO0_FETCH GPIO1_MASTER/ VSS-C SCLK TESTIN TMS MAC/_TESTOUT TD0 MAD7 MAD6 MAD5 MAD4 VDD MAD3 MAD2 MAD1 MAD0 GPIO2_MAS2/ VSS GPIO3 GPIO4 DIFFSENS TGS VDD IGS SELDIR RSTDIR BSYDIR VSS SDIR11 NC NC NC NC NC
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
NC NC NC NC NC C_BE3/ IDSEL BYTEPAR2 AD23 VSS AD22 AD21 AD20 VDD-I AD19 VSS AD18 AD17 AD16 VSS C_BE2/ FRAME/ IRDY/ VSS TRDY/ DEVSEL/ VDD-I STOP/ VSS PERR/ PAR C_BE1/ VSS BYTEPAR1 AD15 AD14 AD13 VSS AD12 VDD-I AD11 AD10 AD9 VSS AD8 C_BE0/ BYTEPAR0 AD7 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
LSI53C875N PCI to SCSI I/O Processor 208-Pin Quad Flat Pack
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
NC NC NC NC NC NC SDIR7 SDIRP0 VDD SD12/ SD13 SD14/ VSS-S SD15/ SDP1/ SD0/ SD1/ VSS-S SD2/ SD3/ SD4/ SD5/ VSS-S SD6/ SD7/ SDP0/ SATN/ VSS-S SBSY/ SACK/ SRST/ SMSG/ SSEL/ VSS-S SC_D/ SREQ/ SI_0/ SD8/ VSS-S SD9/ SD10/ SD11/ VDD SDIR8 SDIR9 SDIR10 NC NC NC NC NC NC
Signal Descriptions
Figure 4.4
A1 C_BE3/ B1 IDSEL C1 AD21 D1 VSS E1 AD16 F1 IRDY/ G1 VDD H1 PAR J1 AD14 K1 VDD-1 L1 AD9 M1 AD7 N1 AD6 N2 VSS C2 AD23 D2 A2 AD24 B2 NC
LSI53C875JB Pin Diagram (Top View)
A3 AD27 B3 VSS C3 VSS D3 AD20 E3 AD18 F3 C_BE2/ G3 TRDY/ H3 C-BE1/ J3 VSS K3 VSS L3 AD4 M3 A4 AD29 B4 AD28 C4 AD26 D4 AD25 E4 AD19 F4 VSS G4 STOP/ H4 VSS J4 AD10 K4 C_BE0/ L4 AD2 M4 VSS N4 AD0 A5 VDD-C B5 AD31 C5 AD30 D5 VDD-1 E5 AD22 F5 VSS G5 VSS H5 AD15 J5 VDD-1 K5 AD1 L5 VDD-C M5 IRQ/ N5 GPIO_ FETCH/ K6 GPIO1_ MASTER/ L6 VSS-C M6 SCLK N6 TMS H5 AD12 J6 TD0 J7 VDD K7 MAD4 L7 MAD7 M7 MAD6 N7 MAD5 A6 CLK B6 RST/ C6 VSS-C D6 GNT/ E6 REQ/ F6 VSS G6 NC H7 NC A7 MCE/ B7 MDE/ C7 MWE/ D7 TDI E7 SERR/ F7 NC G7 NC H8 DIFFSENS J8 GPIO_ MAS2/ K8 MAD0 L8 MAD1 M8 MAD3 N8 MAD2 L9 GPIO4 M9 GPIO3 N9 VSS A8 MAS0/ B8 MAS1/ C8 SDIR12 D8 SDIR13 E8 VDD F8 SDP1/ G8 NC A9 VSS B9 SDIR14 C9 SDIR15 D9 SDIR0 E9 SDIR3 F9 SD2/ G9 SD6/ H9 SBSY/ J9 SD11/ K9 IGS A10 TCK B10 VDD C10 SDIR1 D10 SDIRP0 E10 SD14/ F10 SD3/ G10 SD7/ H10 SSEL/ J10 SD8/ K10 VSS L10 RSTDIR M10 VDD N10 TGS A11 SDIR2 B11 VSS C11 SDIR4 D11 SD12 E11 SD0/ F11 SD4/ G11 VSS-S H11 SMSG/ J11 SREQ/ K11 SD9/ L11 VDD-S M11 BSYDIR N11 SELDIR A12 SDIR5 B12 NC C12 VDD-S D12 VSS-S E12 SD1/ F12 VSS-S G12 SATN/ H12 SRST/ J12 SC_D/ K12 VSS-S L12 SDIR8 M12 NC N12 SDIR11 A13 SDIR6 B13 SDIR7 C13 SD13/ D13 SD15/ E13 VSS-S F13 SD5/ G13 SDP0/ H13 SACK/ J13 VSS-S K13 SI_0/ L13 SD10/ M13 SDIR9 N13 SDIR10
VDD-1 E2 AD17 F2 FRAME/ G2 DEVSEL/ H2 PERR/ J2 AD13 K2 AD11 L2 AD8 M2 NC
AD5 N3 AD3
4-5
Note: Pins F7, G6, G7, G8, and H7 are connected to the die pad.
The PCI/SCSI pin definitions are organized into the following functional groups: System, Address/Data, Interface Control, Arbitration, Error Reporting, SCSI, and Optional Interface. A slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a LOW voltage. When the slash is absent, the signal is active at a HIGH voltage. There are four signal type definitions:
I O T/S S/T/S Input, a standard input-only signal. Output, a standard output driver (typically a Totem Pole Output). 3-state, a bidirectional, 3-state input/output signal. Sustained 3-state, an active LOW 3-state signal owned and driven by one and only one agent at a time.
4-6
Signal Descriptions
Table 4.1 describes the LSI53C875, LSI53C875J, LSI53C875E, and LSI53C875JE Power and Ground Signals group. Table 4.1 LSI53C875, LSI53C875J, LSI53C875E, and LSI53C875JE Power and Ground Signals
Pin No. 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 123, 133, 152, 158 63, 74, 84, 118, 128, 138 8, 21, 33, 45, 155 88, 93, 99, 104, 109, 114 55, 146 51, 149 Description Ground to the PCI I/O pins.
Name VSS
VDD VDD-I1 VSS-S VSS-C VDD-C
Power supplies to the Standard I/O pins. VDD pad for PCI I/O pins. Ground to the SCSI bus I/O pins. Ground to the internal logic core. Power supplies to the internal logic core.
1. These pins can accept a VDD source of 3.3 V or 5 V. All other VDD pins must be supplied 5 V.
Table 4.2 describes the LSI53C875N Power and Ground Signals group. Table 4.2
Name VSS
LSI53C875N Power and Ground Signals
Pin No. 10, 16, 20, 24, 29, 33, 38, 44, 59, 65, 88, 98, 164, 175, 196, 202 82, 93, 148, 169, 180 14, 27, 62, 199 118, 123, 129, 134, 139, 144 72, 189 68, 192 Description Ground to the PCI I/O pins.
VDD VDD-I1 VSS-S VSS-C VDD-C
Power supplies to the Standard I/O pins. VDD pad for PCI I/O pins. Ground to the SCSI bus I/O pins. Ground to the internal logic core. Power supplies to the internal logic core.
1. These pins can accept a VDD source of 3.3 V or 5 V. All other VDD pins must be supplied 5 V.
4-7
Table 4.3 describes the LSI53C875JB and LSI53C875JBE Power and Ground Signals group. Table 4.3 LSI53C875JB and LSI53C875JBE Power and Ground Signals
Pin No. A9, B3, B11, C3, D1, F4, F5, F6, G5, H4, J3, K3, K10, M4, N2, N9 B10, E8, J7, M10 D2, D5, G1, J5, K1 C12, L11 L6, C6 A5, L5 Description Ground to the PCI I/O pins.
Name VSS
VDD VDD-I1 VDD-S VSS-C VDD-C
Power supplies to the Standard I/O pins. VDD pad for PCI I/O pins. Ground to the SCSI bus I/O pins. Ground to the internal logic core. Power supplies to the internal logic core.
1. These pins can accept a VDD source of 3.3 V or 5 V. All other VDD pins must be supplied 5 V.
4-8
Signal Descriptions
Figure 4.5 is the functional signal grouping for the LSI53C875. Figure 4.5 LSI53C875 Functional Signal Grouping
LSI53C875 System CLK RST SCLK SD[15:0] SDP[1:0] SCTRL SDIR[15:0] SDIRP[1:0] SELDIR RSTDIR BSYDIR IGS TGS TESTIN/ GPIO0_FETCH/ GPIO1_MASTER/ GPIO3 DIFFSENS MAC/_TESTOUT IRQ/ BIG_LIT/ MAS0/ MAS1/ MAD[7:0] MWE/ MOE/ MCE/ GPIO2_MAS2/
Address and Data
AD[31:0] C_BE[3:0]/ PAR FRAME/ TRDY/ IRDY/ STOP/ DEVSEL/ IDSEL REQ/ GNT/ PERR/ SERR/
SCSI
Interface Control
Arbitration Error Reporting
Additional Interface
External Memory Interface
4-9
Table 4.4 describes the System Signals group. Table 4.4 System Signals
Pin No. LSI53C875, LSI53C875J, LSI53C875N, Name LSI53C875JB CLK 145/188/A6
Typ e I
Description Clock provides timing for all transactions on the PCI bus and is an input to every PCI device. All other PCI signals are sampled on the rising edge of CLK, and other timing parameters are defined with respect to this edge. Clock can optionally serve as the SCSI core clock, but this may effect the fast SCSI transfer rates. Reset forces the PCI sequencer of each device to a known state. All T/S and S/T/S signals are forced to a high impedance state, and all internal logic is reset. The RST/ input is synchronized internally to the rising edge of CLK. The CLK input must be active while RST/ is active to properly reset the device.
RST/
144/187/B6
I
4-10
Signal Descriptions
Table 4.5 describes the Address and Data Signals group. Table 4.5 Address and Data Signals
Typ e T/S
Name AD[31:0]
Pin No. LSI53C875 LSI53C875J: 150, 151, 153, 154, 156, 157, 159, 160, 3, 5, 6, 7, 9, 11, 12, 13, 28, 29, 30, 32, 34, 35, 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 LSI53C875N: 194, 195, 197, 198, 200, 201, 203, 204, 9, 11, 12, 13, 15, 17, 18, 19, 35, 36, 37, 39, 41, 42, 43, 45, 48, 58, 60, 61, 63, 64, 66, 67 LSI53C875JB: B5, C5, A4, B4, A3, C4, D4, A2, C2, E5, C1, D3, E4, E3, E2, E1, H5, J1, J2, H6, K2, J4, L1, L2, M1, N1, M3, L3, N3, L4, K5, N4
Description Physical longword Address and Data are multiplexed on the same PCI pins. During the first clock of a transaction, AD[31:0] contain a physical address. During subsequent clocks, AD[31:0] contain data. A bus transaction consists of an address phase, followed by one or more data phases. PCI supports both read and write bursts. AD[7:0] define the least significant byte, and AD[31:24] define the most significant byte.
C_BE[3:0]/
LSI53C875 LSI53C875J: 1, 15, 26, 39 LSI53C875N: 6, 21, 32, 46 LSI53C875JB: A1,F3, H3, K4
T/S
Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C_BE[3:0]/ define the bus command. During the data phase, C_BE[3:0]/ are used as byte enables. The byte enables determine which byte lanes carry meaningful data. C_BE[0]/ applies to byte 0, and C_BE[3]/ to byte 3.
4-11
Table 4.5
Address and Data Signals (Cont.)
Typ e T/S
Name PAR
Pin No. LSI53C875, LSI53C875J: 25 LSI53C875N: 31 LSI53C875JB: H1
Description Parity is the even parity bit that protects the AD[31:0] and C_BE[3:0]/ lines. During address phase, both the address and command bits are covered. During data phase, both data and byte enables are covered.
BYTEPAR[3:0] (LSI53C875N only)
193, 8, 34, 47
T/S
When the PCI Byte Parity pins are enabled, the LSI53C875N checks each byte of incoming data on the PCI bus against its corresponding parity line, in addition to the normal parity checking against the PCI PAR signal. This extra parity checking/generation is always enabled for the LSI53C875N. Is not register selectable. A parity error on any Byte Parity pin for PCI master read or slave write operation causes a fatal DMA interrupt and SCRIPTS stops running. Mask this interrupt with the Extended Byte Parity Enable bit, bit 1 of the DMA Interrupt Enable (DIEN) register.
Table 4.6 describes the Interface Control Signals group. Table 4.6 Interface Control Signals
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 16/22/F2
Name FRAME/
Type
Description
S/T/S Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted to indicate a bus transaction is beginning. While FRAME/ is asserted, data transfers continue. When FRAME/ is deasserted, the transaction is in the final data phase or the bus is idle. S/T/S Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. TRDY/ is used with IRDY/. A data phase is completed on any clock when both TRDY/ and IRDY/ are sampled asserted. During a read, TRDY/ indicates that valid data is present on AD[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY/ and TRDY/ are asserted together.
TRDY/
19/25/G3
4-12
Signal Descriptions
Table 4.6
Interface Control Signals (Cont.)
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 17/23/F1
Name IRDY/
Type
Description
S/T/S Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. IRDY/ is used with TRDY/. A data phase is completed on any clock when both IRDY/ and TRDY/ are sampled asserted. During a write, IRDY/ indicates that valid data is present on AD[31:0]. During a read, it indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY/ and TRDY/ are asserted together. S/T/S Stop indicates that the selected target is requesting the master to stop the current transaction. S/T/S Device Select indicates that the driving device has decoded its address as the target of the current access. As an input, it indicates to a master whether any device on the bus has been selected. I Initialization Device Select is used as a chip select in place of the upper 24 address lines during configuration read and write transactions.
STOP/ DEVSEL/
22/28/G4 20/26/G2
IDSEL
2/7/B1
Table 4.7 describes the Arbitration Signals group. Table 4.7 Arbitration Signals
Pin No. LSI53C875, LSI53C875J, LSI53C875N, Name LSI53C875JB REQ/ 148/191/E6
Typ e O
Description Request indicates to the system arbiter that this agent desires use of the PCI bus. This is a point-to-point signal. Every master has its own REQ/ signal. Grant indicates to the agent that access to the PCI bus has been granted. This is a point-to-point signal. Every master has its own GNT/ signal.
GNT/
147/190/D6
I
4-13
Table 4.8 describes the Error Reporting Signals group. Table 4.8 Error Reporting Signals
Name PERR/
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 24/30/H2
Type
Description
S/T/S Parity Error may be pulsed active by an agent that detects a data parity error. PERR/ can be used by any agent to signal data corruptions. O System Error is an open drain output used to report address parity errors. On detection of a PERR/ pulse, the central resource generates a nonmaskable interrupt to the host CPU, which often implies the system is unable to continue operation once error processing completes.
SERR/
143/186/E7
4-14
Signal Descriptions
Table 4.9 describes the SCSI Signals group. Table 4.9 SCSI SIgnals
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 56/73/M6
Name SCLK
Type I
Description SCSI Clock is used to derive all SCSI-related timings. The speed of this clock is determined by the application's requirements. In some applications SCLK may be sourced internally from the PCI bus clock (CLK). If SCLK is internally sourced, then the SCLK pin should be tied LOW. SCSI Data includes the following data lines and parity signals: SD[15:0]/ (16-bit SCSI data bus), and SDP[1:0]/ (SCSI data parity bits).
SD[15:0]/, SDP[1:0]/
LSI53C875, LSI53C875J: 113, 115, 116, 117, 85, 86, 87, 89, 102, 103, 105, 106, 107, 108, 110, 111, 112, 101 LSI53C875N: 143, 145, 146, 147, 115, 116, 117, 119, 132, 133, 135, 136, 137, 138, 140, 141, 142, 131 LSI53C875JB: D13, E10, C13, D11, J9, L13 K11, J10, G10, G9, F13, F11, F10, F9, E12, E11, F8, G13
I/O
4-15
Table 4.9
SCSI SIgnals (Cont.)
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB LSI53C875, LSI53C875J: 92, 90, 95, 91, 97, 98, 100, 96, 94 LSI53C875N: 122, 120, 125, 121, 127, 128, 130, 126, 124 LSI53C875JB: J12, K13, H11, J11, H13, H9, G12, H12, H10
Name SCTRL/
Type I/O
Description SCSI Control includes the following signals: SC_D/ SCSI phase line, command/data SI_O/ SCSI phase line, input/output SMSG/ SCSI phase line, message SREQ/ Data handshake signal from target device SACK/ Data handshake signal from initiator device SBSY/ SCSI bus arbitration signal, busy SATN/ SCSI Attention, the initiator is requesting a message out phase SRST/ SCSI bus reset SSEL/ SCSI bus arbitration signal, select device
SDIR[15:0]
LSI53C875, LSI53C875J: 131, 132, 134, 135, 80, 81, 82, 83, 120, 121, 122, 124, 125, 126, 127, 129 LSI53C875N: 173, 174, 176, 177, 99, 111, 112, 113, 150, 162, 163, 165, 166, 167, 168, 170 LSI53C875JB: C9, B9, D8, C8, N12, N13, M13, L12, B13, A13, A12, C11, E9, A11, C10, D9
O
Driver direction control for SCSI data lines.
4-16
Signal Descriptions
Table 4.9
SCSI SIgnals (Cont.)
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 130, 119; NA, 119/171, 149/NA, D10
Name SDIRP[1:0] (SDIPR1 is not available on LSI53C875J, LSI53C875JB)
Type O
Description Driver direction control for SCSI parity signals. In the LSI53C875J and LSI53C875JB, this pin is replaced by the TCK JTAG signal. If the device is used in a wide differential system, use the SDIRP0 pin to control the direction of the differential transceiver for both the SP0 and SP1 signals. The SDIRP0 signal is capable of driving both direction inputs from a transceiver. Driver Enable Control for SCSI SEL/ signal. Driver Enable Control for SCSI RST/ signal. Driver Enable Control for SCSI BSY/ signal. Direction Control for initiator driver group. Direction Control for target driver group.
SELDIR RSTDIR BSYDIR IGS TGS
76/95/N11 77/96/L10 78/97/M11 75/94/K9 73/92/N10
O O O O O
4-17
Table 4.10 describes the Additional Interface Signals group. Table 4.10 Additional Interface Signals
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 57, NA/74/NA
Name TESTIN (Not available on LSI53C875J, LSI53C875JB)
Type Description I Test In. When this pin is driven LOW, the LSI53C875 connects all inputs and outputs to an "AND tree." The SCSI control signals and data lines are not connected to the "AND tree." The output of the "AND tree" is connected to the Test Out pin. This allows manufacturers to verify chip connectivity and determine exactly which pins are not properly attached. When the TESTIN pin is driven LOW, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals will be 3-stated, and the MAC/_TESTOUT pin will be enabled. Connectivity can be tested by driving one of the LSI53C875 pins LOW. The MAC/_TESTOUT pin should respond by also driving LOW. General Purpose I/O pin. Optionally, when driven LOW, this pin indicates that the next bus request will be for an opcode fetch. This pin powers up as a general purpose input. This pin has two specific purposes in the LSI Logic SDMS software. SDMS software uses it to toggle SCSI device LEDs, turning on the LED whenever the LSI53C875 is on the SCSI bus. SDMS software drives this pin LOW to turn on the LED, or drives it HIGH to turn off the LED. This signal can also be used as data I/O for serial EEPROM access. In this case it is used with the GPIO0 pin, which serves as a clock, and the pin can be controlled from PCI configuration register 0x35 or observed from the General Purpose (GPREG) operating register, at address 0x07. General Purpose I/O pin. Optionally, when driven LOW, indicates that the LSI53C875 is bus master. This pin powers up as a general purpose input. LSI Logic SDMS software supports use of this signal in serial EEPROM applications, when enabled, in combination with the GPIO0 pin. When this signal is used as a clock for serial EEPROM access, the GPIO1 pin serves as data, and the pin is controlled from PCI configuration register 0x35.
GPIO0_ FETCH/
53/70/N5
I/O
GPIO1_ MASTER/
54/71/K6
I/O
4-18
Signal Descriptions
Table 4.10
Additional Interface Signals (Cont.)
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 71, 70/90, 89/L9, M9
Name GPIO[4:3]
Type Description I/O General Purpose I/O pins. GPIO4 powers up as an output. It can be used as the enable line for VPP, the 12 V power supply to the external Flash memory interface. GPIO3 powers up as an input. LSI Logic SDMS software uses GPIO3 to detect a differential board. If the pin is pulled LOW externally, the board is configured by SDMS software as a differential board. If it is pulled HIGH or left floating, SDMS software configures it as an SE board. The LSI Logic PCI to SCSI host adapters use the GPIO4 pin in the process of flashing a new SDMS software ROM. The Differential Sense pin detects the presence of an SE device on a differential system. When external differential transceivers are used and a zero is detected on this pin, all chip SCSI outputs will be 3-stated to avoid damage to the transceivers. This pin should be tied HIGH during SE operation. The normal value of this pin is 1. Memory Access Control. This pin can be programmed to indicate local or system memory accesses (non-PCI applications). It is also used to test the connectivity of the LSI53C875 signals using an "AND tree" scheme. The MAC/_TESTOUT pin is only driven as the Test Out function when the TESTIN/ pin is driven LOW. Interrupt. This signal, when asserted LOW, indicates that an interrupting condition has occurred and that service is required from the host CPU. The output drive of this pin is programmed as either open drain with an internal weak pull-up or, optionally, as a totem pole driver. Refer to the description of DMA Control (DCNTL) register, bit 3, for additional information.
DIFFSENS
72/91/H8
I
MAC/_ TESTOUT (Not available on LSI53C875, LSI53C875JB) IRQ/
58, NA/76/NA
T/S
52/69/M5
O
4-19
Table 4.10
Additional Interface Signals (Cont.)
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 142, NA/184/NA
Name BIG_LIT/ (Not available on LSI53C875J, LSI53C875JB)
Type Description I Big_Little Endian Select. When this pin is driven LOW, the LSI53C875 routes the first byte of an aligned SCSI to PCI transfer to byte lane zero of the PCI bus and subsequent bytes received are routed to ascending lanes. An aligned PCI to SCSI transfer routes PCI byte lane zero onto the SCSI bus first, and transfers ascending byte lanes in order. When this pin is driven HIGH, the LSI53C875 routes the first byte of an aligned SCSI-to-PCI transfer to byte lane three of the PCI bus and subsequent bytes received are routed to descending lanes. An aligned PCI-to-SCSI transfer routes PCI byte lane three onto the SCSI bus first and transfers descending byte lanes in order. This mode of operation also applies to the external memory interface. When this pin is driven in little endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to PCI byte lane zero and the data accessed at location 0x00003 is routed to PCI byte lane three. When the chip is performing a write to Flash memory, PCI byte lane zero is routed to location 0x00000 and ascending byte lanes are routed to subsequent memory locations. When this pin is driven in big endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to PCI byte lane three and the data accessed at location 0x00003 is routed to byte lane zero. When the chip is performing a write to Flash memory, PCI byte lane three is routed to location 0x00000 and descending byte lanes are routed to subsequent memory locations.
4-20
Signal Descriptions
Table 4.11 describes the External Memory Interface Signals group. Table 4.11 External Memory Interface Signals
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 137/179/A8
Name MAS0/
Typ e O
Description Memory Address Strobe 0. This pin is used to latch in the least significant address byte of an external EPROM or Flash memory. Since the LSI53C875 moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which are used to assemble up to a 20-bit address for the external memory. Memory Address Strobe 1. This pin is used to latch in the address byte corresponding to address bits [15:8] of an external EPROM or Flash memory. Since the LSI53C875A moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which assemble up to a 20-bit address for the external memory. Memory Address/Data Bus. This bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external EPROM or Flash memory. This bus will put out the most significant byte first and finish with the least significant bits. It is also used to write data to a Flash memory or read data into the chip from external EPROM/Flash memory. See Section 4.1, "MAD Bus Programming," for more details.
MAS1/
136/178/B8
O
MAD[7:0]
LSI53C875, LSI53C875E, LSI53C875J, LSI53C875JE: 59, 60, 61, 62, 64, 65, 66, 67 59, 60, 61, 62, 64, 65, 66, 67 LSI53C875N: 78, 79, 80, 81, 83, 84, 85, 86 LSI53C875JB, LSI53C875JB E: L7, M7, N7, K7, M8, N8, L8, K8
I/O
MWE/ MOE/
139/181/C7 140/182/B7
O O
Memory Write Enable. This pin is used as a write enable signal to an external Flash memory. Memory Output Enable. This pin is used as an output enable signal to an external EPROM or Flash memory during read operations. Memory Chip Enable. This pin is used as a chip enable signal to an external EPROM or Flash memory device.
MCE/
141/183/A7
O
4-21
Table 4.11
External Memory Interface Signals (Cont.)
Pin No. LSI53C875, LSI53C875J, LSI53C875N, LSI53C875JB 68 /87/J8
Name GPIO2_ MAS2/
Typ e I/O
Description General Purpose I/O pin. Optionally, this pin is used as a Memory Address Strobe 2 if an external memory with more than 16 bits of addressing is specified by the pull-down resistors at power-up and bit 0 in the Expansion ROM Base Address register is set.
Table 4.12 describes the JTAG Signals group for the LSI53C875J, LSI53C875N, and LSI53C875JB.
Table 4.12
JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB Only)
Pin No. LSI53C875J, LSI53C875N, LSI53C875JB 130/172/A10 57/75/N6 142/185/D7 58/77/J6
Name TCK TMS TDI TDO
Type - - - -
Description Test Clock pin for JTAG boundary scan. Test Mode Select pin for JTAG boundary scan. Test Data In pin for JTAG boundary scan. Test Data Out pin for JTAG boundary scan.
4.1 MAD Bus Programming
The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, are also used to program power-up options for the chip. A particular option is programmed by connecting a 4.7 k resistor between the appropriate MAD[x] pin and Vss. The pull-down resistors require that HC or HCT external components are used for the memory interface.
*
MAD[7] has no functionality. Do not place a pull-down resistor on this pin.
4-22
Signal Descriptions
* * *
MAD[6] Subsystem Data configuration. Refer to Table 4.13 and Table 4.14 for the different configurations. MAD[5] SCRIPTS RAM disable. Connecting a 4.7 k resistor between MAD[5] and Vss disables SCRIPTS RAM. MAD[4] Subsystem Data configuration. Refer to Table 4.13 and Table 4.14 for the different configurations.
Table 4.13
Subsystem Data Configuration Table for the LSI53C875E (PCI Rev ID 0x26)
Normal 4-hi, 6-hi 0x1000 0x000F 0x1000 0x1000 Read/Write 4-hi, 6-lo 0x1000 0x000F 0x0000 0x0000 Reserved 4-low, 6-hi - - - - LSI Logic 4-low, 6-lo 0x1000 0x000F 0x0000 0x0000
Mode MAD Pins Vendor ID Device ID Subsystem Vendor ID Subsystem ID
Offset 0x00 0x02 0x2C 0x2E
Table 4.14
Subsystem Data Configuration Table for the LSI53C875 (PCI Rev ID 0x04), Revision G Only
Normal 4-hi, 6-hi 0x1000 0x000F 0x1000 0x1000 Read/Write 4-hi, 6-lo 0x1000 0x000F 0x0000 0x0000 Reserved 4-low, 6-hi - - - - LSI Logic 4-low, 6-lo 0x1000 0x000F 0x0000 0x0000
Mode MAD Pins Vendor ID Device ID Subsystem Vendor ID Subsystem ID
Offset 0x00 0x02 0x2C 0x2E
Note:
The chip revisions before Revision G of the LSI53C875 (PCI Rev ID 0x04) do not support different Subsystem Data Configurations. The Subsystem ID (SSID) and Subsystem Vendor ID (SSVID) registers are hard wired to zero values.
*
MAD[3:1] used to set the size of the external expansion ROM device attached. Encoding for these pins are listed in Table 4.15.
MAD Bus Programming
4-23
Table 4.15
External Memory Support
Available Memory Space 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 1024 Kbytes No external memory present
MAD[3:1] 000 001 010 011 100 101 110 111
*
MAD[0] Slow ROM pin. When pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. Note: All MAD pins have internal pull-up resistors.
4-24
Signal Descriptions
Chapter 5 SCSI Operating Registers
This section contains descriptions of all LSI53C875 operating registers. Table 5.1 lists registers by operating and configuration addresses. The terms "set" and "assert" are used to refer to bits that are programmed to a binary one. Similarly, the terms "deassert," "clear," and "reset" are used to refer to bits that are programmed to a binary zero. Any bits marked as reserved should always be written to zero; mask all information read from them. Reserved bit functions may be changed at any time. Unless otherwise indicated, all bits in registers are active HIGH, that is, the feature is enabled by setting the bit. The bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. Note: The only register that the host CPU can access while the LSI53C875 is executing SCRIPTS is the Interrupt Status (ISTAT) register. Attempts to access other registers interferes with the operation of the chip. However, all operating registers are accessible with SCRIPTS. All read data is synchronized and stable when presented to the PCI bus. The LSI53C875 cannot fetch SCRIPTS instructions from the operating register space. Instructions must be fetched from system memory or the internal SCRIPTS RAM.
LSI53C875/875E PCI to Ultra SCSI I/O Processor
5-1
.
Table 5.1
31 SCNTL3 GPREG SBCL SSTAT2
LSI53C875 Register Map
16 15 SCNTL2 SDID SSID SSTAT1 DSA Reserved CTEST2 TEMP CTEST5 DNAD DSP DSPS SCRATCH A SCNTL1 SXFER SOCL SSTAT0 SCNTL0 SCID SFBR DSTAT ISTAT Reserved DFIFO 0 Mem I/O 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C Config 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC
CTEST3 CTEST6 DCMD
CTEST1 CTEST4 DBC
DCNTL SIST1 GPCNTL RESPID1 STEST3 Reserved Reserved Reserved
SBR ADDER SIST0 MACNTL RESPID0 STEST2
DIEN SIEN1 SWIDE STIME1 STEST1 SIDL SODL SBDL SCRATCH B SCRATCH C SCRATCH D SCRATCH E SCRATCH F SCRATCH G SCRATCH H SCRATCH I SCRATCH J
DMODE SIEN0 SLPAR STIME0 STEST0
5-2
SCSI Operating Registers
Register: 0x00 (0x80)
SCSI Control Zero (SCNTL0) Read/Write
7 ARB[1:0] 1 1 6 5 START 0 4 WATN 0 3 EPC 0 2 R x 1 AAP 0 0 TRG 0
ARB1[1:0]
Arbitration Mode Bits 1 and 0
ARB1 0 0 1 1 ARB0 0 1 0 1 Arbitration Mode Simple arbitration Reserved Reserved Full arbitration, selection/reselection
[7:6]
Simple Arbitration 1. The LSI53C875 waits for a bus free condition to occur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus. If the SSEL/ signal is asserted by another SCSI device, the LSI53C875 deasserts SBSY/, deasserts its ID, and sets the Lost Arbitration bit (bit 3) in the SCSI Status Zero (SSTAT0) register. 3. After an arbitration delay, the CPU should read the SCSI Bus Data Lines (SBDL) register to check if a higher priority SCSI ID is present. If no higher priority ID bit is set, and the Lost Arbitration bit is not set, the LSI53C875 wins arbitration. 4. Once the LSI53C875 wins arbitration, SSEL/ must be asserted using the SCSI Output Control Latch (SOCL) for a bus clear plus a bus settle delay (1.2 s) before a low level selection is performed. Full Arbitration, Selection/Reselection 1. The LSI53C875 waits for a bus free condition.
5-3
2. It asserts SBSY/ and its SCSI ID (the highest priority ID stored in the SCSI Chip ID (SCID) register) onto the SCSI bus. 3. If the SSEL/ signal is asserted by another SCSI device or if the LSI53C875 detects a higher priority ID, the LSI53C875 deasserts BSY, deasserts its ID, and waits until the next bus free state to try arbitration again. 4. The LSI53C875 repeats arbitration until it wins control of the SCSI bus. When it wins, the Won Arbitration bit is set in the SCSI Status Zero (SSTAT0) register, bit 2. 5. The LSI53C875 performs selection by asserting the following onto the SCSI bus: SSEL/, the target's ID (stored in the SCSI Destination ID (SDID) register), and the LSI53C875's ID (stored in the SCSI Chip ID (SCID) register). 6. After a selection is complete, the Function Complete bit is set in the SCSI Interrupt Status Zero (SIST0) register, bit 6. 7. If a selection time-out occurs, the Selection Time-Out bit is set in the SCSI Interrupt Status One (SIST1) register, bit 2. START Start Sequence 5 When this bit is set, the LSI53C875 starts the arbitration sequence indicated by the Arbitration Mode bits. The Start Sequence bit is accessed directly in low level mode; during SCSI SCRIPTS operations, this bit is controlled by the SCRIPTS processor. Do not start an arbitration sequence if the connected (CON) bit in the SCSI Control One (SCNTL1) register, bit 4, indicates that the LSI53C875 is already connected to the SCSI bus. This bit is automatically cleared when the arbitration sequence is complete. If a sequence is aborted, check bit 4 in the SCSI Control One (SCNTL1) register to verify that the LSI53C875 is not connected to the SCSI bus. Select with SATN/ on a Start Sequence 4 When this bit is set and the LSI53C875 is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C875 has a message to send. If a selection
WATN
5-4
SCSI Operating Registers
time-out occurs while attempting to select a target device, SATN/ is deasserted at the same time SSEL/ is deasserted. When this bit is cleared, the SATN/ signal is not asserted during selection. When executing SCSI SCRIPTS, this bit is controlled by the SCRIPTS processor, but manual setting is possible in low level mode. EPC Enable Parity Checking 3 When this bit is set, the SCSI data bus is checked for odd parity when data is received from the SCSI bus in either initiator or target mode. Parity is also checked as data goes from the SCSI FIFO to the DMA FIFO. If a parity error is detected, bit 0 of the SCSI Interrupt Status Zero (SIST0) register is set and an interrupt may be generated. If the LSI53C875 is operating in the initiator mode and a parity error is detected, assertion of SATN/ is optional, but the transfer continues until the target changes phase. When this bit is cleared, parity errors are not reported. When these bits are set in the LSI53C875N, the chip again checks inbound SCSI parity at the SCSI FIFO- DMA FIFO interface after the data has passed through the SCSI FIFO. The parity bits are not passed through the DMA FIFO, but parity is generated before the data is sent out on the PCI bus. R AAP Reserved 2
Assert SATN/ on Parity Error 1 When this bit is set, the LSI53C875 automatically asserts the SATN/ signal upon detection of a parity error. SATN/ is only asserted in the initiator mode. The SATN/ signal is asserted before deasserting SACK/ during the byte transfer with the parity error. Also set the Enable Parity Checking bit for the LSI53C875 to assert SATN/ in this manner. A parity error is detected on data received from the SCSI bus. If the Assert SATN/ on Parity Error bit is cleared or the Enable Parity Checking bit is cleared, SATN/ is not automatically asserted on the SCSI bus when a parity error is received.
5-5
TRG
Target Mode 0 This bit determines the default operating mode of the LSI53C875. The user must manually set the target or initiator mode. This is done using the SCRIPTS language (SET TARTET or CLEAR TARGET). When this bit is set, the chip is a target device by default. When this bit is cleared, the LSI53C875 is an initiator device by default. Writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes.
Note:
Register: 0x01 (0x81)
SCSI Control One (SCNTL1) Read/Write
7 EXC 0 6 ADB 0 5 DHP 0 4 CON 0 3 RST 0 2 AESP 0 1 IARB 0 0 SST 0
EXC
Extra Clock Cycle of Data Setup 7 When this bit is set, an extra clock period of data setup is added to each SCSI send data transfer. The extra data setup time can provide additional system design margin, though it affects the SCSI transfer rates. Clearing this bit disables the extra clock cycle of data setup time. Setting this bit only affects SCSI send operations. Assert SCSI Data Bus 6 When this bit is set, the LSI53C875 drives the contents of the SCSI Output Data Latch (SODL) onto the SCSI data bus. When the LSI53C875 is an initiator, the SCSI I/O signal must be inactive to assert the SCSI Output Data Latch (SODL) contents onto the SCSI bus. When the LSI53C875 is a target, the SCSI I/O signal must be active to assert the SODL contents onto the SCSI bus. The contents of the SCSI Output Data Latch (SODL) register can be asserted at any time, even before the LSI53C875 is connected to the SCSI bus. Clear this bit when executing SCSI SCRIPTS. It is normally used only for diagnostics testing or operation in low level mode.
ADB
5-6
SCSI Operating Registers
DHP
Disable Halt on Parity Error or ATN (Target Only) 5 The DHP bit is only defined for target mode. When this bit is cleared, the LSI53C875 halts the SCSI data transfer when a parity error is detected or when the SATN/ signal is asserted. If SATN/ or a parity error is received in the middle of a data transfer, the LSI53C875 may transfer up to three additional bytes before halting to synchronize between internal core cells. During synchronous operation, the LSI53C875 transfers data until there are no outstanding synchronous offsets. If the LSI53C875 is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C875 does not halt the SCSI transfer when SATN/ or a parity error is received.
CON
Connected 4 This bit is automatically set any time the LSI53C875 is connected to the SCSI bus as an initiator or as a target. It is set after the LSI53C875 successfully completes arbitration or when it has responded to a bus-initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode. When this bit is cleared, the LSI53C875 is not connected to the SCSI bus. The CPU can force a connected or disconnected condition by setting or clearing this bit. This feature is used primarily during loopback mode.
RST
Assert SCSI RST/ Signal Setting this bit asserts the SRST/ signal. The SRST/ output remains asserted until this bit is cleared. The 25 s minimum assertion time defined in the SCSI specification must be timed out by the controlling microprocessor or a SCRIPTS loop.
3
AESP
Assert Even SCSI Parity (force bad parity) 2 When this bit is set, the LSI53C875 asserts even parity. It forces a SCSI parity error on each byte sent to the SCSI bus from the chip. If parity checking is enabled, then the LSI53C875 checks data received for odd parity. This bit is used for diagnostic testing and should be cleared for normal operation. It is useful to generate parity errors to test error handling functions.
5-7
IARB
Immediate Arbitration 1 Setting this bit causes the SCSI core to immediately begin arbitration once a Bus Free phase is detected following an expected SCSI disconnect. This bit is useful for multithreaded applications. The ARB[1:0] bits in SCSI Control Zero (SCNTL0) register are set for full arbitration and selection before setting this bit. Arbitration is retried until won. At that point, the LSI53C875 holds BSY and SEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out. An unexpected disconnect condition clears IARB without attempting arbitration. See the SCSI Disconnect Unexpected bit (SCSI Control Two (SCNTL2), bit 7) for more information on expected versus unexpected disconnects. During the time between the setting of the IARB bit and the completion of a Select/Reselect instruction, DMA interrupts are disabled. Therefore, interrupt instructions that are issued during this time period will not execute. It is possible to abort an immediate arbitration sequence. First, set the Abort bit in the Interrupt Status (ISTAT) register. Then one of two things eventually happens:
* The Won Arbitration bit (SCSI Status Zero (SSTAT0),
bit 2) will be set. In this case, the Immediate Arbitration bit needs to be cleared. This completes the abort sequence and disconnects the chip from the SCSI bus. If it is not acceptable to go to Bus Free phase immediately following the arbitration phase, it is possible to perform a low level selection instead.
* The abort completes because the LSI53C875 loses
arbitration. This is detected by the clearing of the Immediate Arbitration bit. Do not use the Lost Arbitration bit (SCSI Status Zero (SSTAT0), bit 3) to detect this condition. Take no further action in this case. SST Start SCSI Transfer 0 This bit is automatically set during SCRIPTS execution and should not be used. It causes the SCSI core to begin a SCSI transfer, including SREQ/SACK handshaking.
5-8
SCSI Operating Registers
The determination of whether the transfer is a send or receive is made according to the value written to the I/O bit in SCSI Output Control Latch (SOCL). This bit is self-clearing. Do not set it for low level operation. Note: Writing to this register while not connected may cause the loss of a selection/reselection by resetting the Connected bit.
Register: 0x02 (0x82)
SCSI Control Two (SCNTL2) Read/Write
7 SDU 0 6 CHM 0 5 SLPMD 0 4 SLPHBEN 0 3 WSS 0 2 VUE0 0 1 VUE1 0 0 WSR 0
SDU
SCSI Disconnect Unexpected 7 This bit is valid in the initiator mode only. When this bit is set, the SCSI core is not expecting the SCSI bus to enter the Bus Free phase. If it does, an unexpected disconnect error is generated (see the Unexpected Disconnect bit in the SCSI Interrupt Status Zero (SIST0) register, bit 2). During normal SCRIPTS mode operation, this bit is set automatically whenever the SCSI core is reselected, or successfully selects another SCSI device. The SDU bit should be cleared with a register write (move 0x00 to SCNTL2) before the SCSI core expects a disconnect to occur, normally prior to sending an Abort, Abort Tag, Bus Device Reset, Clear Queue or Release Recovery message, or before deasserting SACK/ after receiving a Disconnect command or Command Complete message. Chained Mode 6 This bit determines whether or not the SCSI core is programmed for chained SCSI mode. This bit is automatically set by the Chained Block Move (CHMOV) SCRIPTS instruction and is automatically cleared by the Block Move SCRIPTS instruction (MOVE). Chained mode is primarily used to transfer consecutive wide data blocks. Using chained mode facilitates partial receive transfers and allows correct partial send behavior. When this bit is set and a data transfer ends on an
CHM
5-9
odd byte boundary, the LSI53C875 stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation, or in the SCSI Output Data Latch (SODL) register during a send operation. This byte is combined with the first byte from the subsequent transfer so that a wide transfer is completed. For more information, see Section 2.5.14, "Chained Block Moves," in Chapter 2, "Functional Description." SLPMD SLPAR Mode Bit 5 If this bit is cleared, the SCSI Longitudinal Parity (SLPAR) register functions like the LSI53C825. If this bit is set, the SCSI Longitudinal Parity (SLPAR) register reflects the high or low byte of the SLPAR word, depending on the state of SCSI Control Two (SCNTL2), bit 4. It also allows a seed value to be written to the SCSI Longitudinal Parity (SLPAR) register. SLPAR High Byte Enable 4 If this bit is cleared, the low byte of the SLPAR word is present in the SCSI Longitudinal Parity (SLPAR) register. If this bit is set, the high byte of the SLPAR word is present in the SCSI Longitudinal Parity (SLPAR) register. Wide SCSI Send 3 When read, this bit returns the value of the Wide SCSI Send (WSS) flag. Asserting this bit clears the WSS flag. This clearing function is self-clearing. When the WSS flag is high following a wide SCSI send operation, the SCSI core is holding a byte of "chain" data in the SCSI Output Data Latch (SODL) register. This data becomes the first low-order byte sent when married with a high-order byte during a subsequent data send transfer. Performing a SCSI receive operation clears this bit. Also, performing any nonwide transfer clears this bit. VUE0 Vendor Unique Enhancements Bit 0 2 This bit is a read only value indicating whether the group code field in the SCSI instruction is standard or vendor unique. If cleared, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. The value in this bit is reloaded at the beginning of all asynchronous target receives. The default for this bit is reset.
SLPHBEN
WSS
5-10
SCSI Operating Registers
VUE1
Vendor Unique Enhancements Bit 1 1 This bit is used to disable the automatic byte count reload during Block Move instructions in the command phase. If this bit is cleared, the device reloads the Block Move byte count if the first byte received is one of the standard group codes. If this bit is set, the device does not reload the Block Move byte count, regardless of the group code. Wide SCSI Receive 0 When read, this bit returns the value of the Wide SCSI Receive (WSR) flag. Setting this bit clears the WSR flag. This clearing function is self-clearing. The WSR flag indicates that the SCSI core received data from the SCSI bus, detected a possible partial transfer at the end of a chained or nonchained block move command, and temporarily stored the high-order byte in the SCSI Wide Residue (SWIDE) register rather than passing the byte out the DMA channel. The hardware uses the WSR status flag to determine what behavior must occur at the start of the next data receive transfer. When the flag is set, the stored data in SWIDE may be "residue" data, valid data for a subsequent data transfer, or overrun data. The byte is read as normal data by starting a data receive transfer. Performing a SCSI send operation clears this bit. Also, performing any nonwide transfer clears this bit.
WSR
5-11
Register: 0x03 (0x83)
SCSI Control Three (SCNTL3) Read/Write
7 ULTRA 0 0 6 SCF[2:0] 0 0 4 3 EWS 0 0 2 CCF[2:0] 0 0 0
ULTRA
Ultra Enable 7 Setting this bit enables Ultra SCSI synchronous SCSI transfers in systems that have an 80 MHz clock. The default value of this bit is 0. This bit should remain cleared in systems that have a 40 MHz clock, unless the SCSI clock doubler is used to increase the SCLK frequency to at least 80 MHz. When this bit is set, the signal filtering period for SREQ/ and SACK/ automatically changes to 15 ns, regardless of the value of the Extend REQ/ACK Filtering bit in the SCSI Test Two (STEST2) register.
SCF[2:0]
Synchronous Clock Conversion Factor [6:4] These bits select a factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic. Write these to the same value as the Clock Conversion Factor bits below unless fast SCSI operation is desired. See the SCSI Transfer (SXFER) register description for examples of how the SCF bits are used to calculate synchronous transfer periods. See the table under the description of bits [7:5] of the SCSI Transfer (SXFER) register for the valid combinations. To migrate from a Fast SCSI-2 system with a 40 MHz clock, divide the clock by a factor of two or more to achieve the same synchronous transfer rate in a system with an 80 MHz clock. For additional information on how the synchronous transfer rate is determined, refer to Chapter 2, "Functional Description." Enable Wide SCSI 3 When this bit is clear, all information transfer phases are assumed to be eight bits, transmitted on SD[7:0]/, SDP0/. When this bit is asserted, data transfers are done 16 bits
Note:
EWS
5-12
SCSI Operating Registers
at a time, with the least significant byte on SD[7:0]/, SDP/ and the most significant byte on SD[15:8]/, SDP1/. Command, Status, and Message phases are not affected by this bit. Clearing this bit will also clear the Wide SCSI Receive bit in the SCSI Control Two (SCNTL2) register, which indicates the presence of a valid data byte in the SCSI Wide Residue (SWIDE) register. CCF[2:0] Clock Conversion Factor [2:0] These bits select a factor by which the frequency of SCLK is divided before being presented to the SCSI core. The synchronous portion of the SCSI core can be run at a different clock rate for fast SCSI, using the Synchronous Clock Conversion Factor bits. The bit encoding is displayed in the table below. All other combinations are reserved and should never be used.
SCF2 CCF2 0 0 0 0 1 1 1 1 SCF1 CCF1 0 0 1 1 0 0 1 1 SCF0 CCF0 0 1 0 1 0 1 0 1 Factor Frequency SCLK/3 SCLK/1 SCLK/1.5 SCLK/2 SCLK/3 SCLK/4 Reserved Reserved SCSI Clock (MHz) 50.01-75.0 16.67-25.0 25.01-37.5 37.51-50.0 50.01-75.0 75.01-80.00 - -
Note:
It is important that these bits be set to the proper values to guarantee that the LSI53C875 meets the SCSI timings as defined by the ANSI specification. For additional information on how the synchronous transfer rate is determined, refer to Chapter 2, "Functional Description." To migrate from a Fast SCSI-2 system with a 40 MHz clock, divide the clock by a factor of two or more to achieve the same synchronous transfer rate in a system with an 80 MHz clock.
5-13
If the SCSI clock doubler is enabled, use the desired frequency after doubling to determine the conversion factor.
Register: 0x04 (0x84)
SCSI Chip ID (SCID) Read/Write
7 R x 6 RRE 0 5 SRE 0 4 R x 0 0 3 ENC 0 0 0
R RRE
Reserved
7
Enable Response to Reselection 6 When this bit is set, the LSI53C875 is enabled to respond to bus-initiated reselection at the chip ID in the Response ID Zero (RESPID0) and Response ID One (RESPID1) registers. Note that the chip does not automatically reconfigure itself to initiator mode as a result of being reselected. Enable Response to Selection 5 When this bit is set, the LSI53C875 is able to respond to bus-initiated selection at the chip ID in the Response ID Zero (RESPID0) and Response ID One (RESPID1) registers. Note that the chip does not automatically reconfigure itself to target mode as a result of being selected. Reserved 4
SRE
R ENC[3:0]
Encoded Chip SCSI ID [3:0] These bits are used to store the LSI53C875 encoded SCSI ID. This is the ID which the chip asserts when arbitrating for the SCSI bus. The IDs that the LSI3C875 responds to when being selected or reselected are configured in the Response ID Zero (RESPID0) and Response ID One (RESPID1) registers. The priority of the 16 possible IDs, in descending order is:
Highest
7 6 5 4 3 2 1 0 15 14 13
Lowest
12 11 10 9 8
5-14
SCSI Operating Registers
Register: 0x05 (0x85)
SCSI Transfer (SXFER) Read/Write
7 TP[2:0] 0 0 0 0 0 5 4 MO[4:0] 0 0 0 0
Note:
When using Table Indirect I/O commands, bits [7:0] of this register are loaded from the I/O data structure.
For additional information on how the synchronous transfer rate is determined, refer to Chapter 2, "Functional Description." TP[2:0] SCSI Synchronous Transfer Period [7:5] These bits determine the SCSI synchronous transfer period used by the LSI53C875 when sending synchronous SCSI data in either initiator or target mode. These bits control the programmable dividers in the chip. For Ultra SCSI transfers, the ideal transfer period is 4, and 5 is acceptable. Setting the transfer period to a value greater than 5 is not recommended.
TP2 0 0 0 0 1 1 1 1 TP1 0 0 1 1 0 0 1 1 TP0 0 1 0 1 0 1 0 1 XFERP 4 5 6 7 8 9 10 11
Note:
The synchronous transfer period the LSI53C875 should use when transferring SCSI data is determined as in this example.
5-15
The LSI53C875 is connected to a hard disk which can transfer data at 10 Mbytes/s synchronously. The LSI53C875's SCLK is running at 40 MHz. The synchronous transfer period (SXFERP) is found as follows: Synchronous Send Rate = (SCLK/SCF)/XFERP Synchronous Receive Rate = (SCKL/SCF)/4. Where:
SCLK SCF SCSI clock. SCSI synchronous core frequency.
Table 5.2
CLK (MHz) 80 80 66.67 66.67 50 50 40 37.50 33.33 25 20 16.67
Examples of Synchronous Transfer Periods for SCSI-1 Transfer Rates
SCSI CLK / SCNTL3 Bits [6:4] 4 4 3 3 2 2 2 1.5 1.5 1 1 1 XFERP (SXFER) Bits [7:5] 4 5 4 5 4 5 4 4 4 4 4 4 Synch. Send Synch. Rate Transfer Synch. Receive (Mbytes/s) Period (ns) Rate (Mbytes) 5 4 5.55 4.44 6.25 5 5 6.25 5.55 6.25 5 4.17 200 250 180 225 160 200 200 160 180 160 200 240 5 5 5.55 5.55 6.25 6.25 5 6.25 5.55 6.25 5 4.17 Synch. Receive Period (ns) 200 200 180 180 160 160 200 160 180 160 200 240
5-16
SCSI Operating Registers
Table 5.3
CLK (MHz) 80 80 66.67 66.67 50 50 40 37.50 33.33 25 20 16.67
Example Transfer Periods for Fast SCSI-2 and Ultra SCSI Transfer Rates
SCSI CLK / SCNTL3 Bits [6:4] 1 2 1.5 1.5 1 1 1 1 1 1 1 1 Synch. Send Synch. Rate Transfer Synch. Receive (Mbytes/s) Period (ns) Rate (Mbytes) 20.0 10.0 11.11 8.88 12.5 10.0 10.0 9.375 8.33 6.25 5 4.17 50 100 90 112.5 80 100 100 106.67 120 160 200 240 20.0 10.0 11.11 11.11 12.5 12.5 10.0 9.375 8.33 6.25 5 4.17 Synch. Receive Period (ns) 50 100 90 90 80 80 100 106.67 120 160 200 240
XFERP 4 4 4 5 4 5 4 4 4 4 4 4
MO[4:0]
Max SCSI Synchronous Offset [4:0] These bits describe the maximum SCSI synchronous offset used by the LSI53C875 when transferring synchronous SCSI data in either initiator or target mode. Table 5.4 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C875. These bits determine the LSI53C875's method of transfer for Data-In and Data-Out phases only. All other information transfers occur asynchronously.
5-17
Table 5.4
MO4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Maximum Synchronous Offset
MO3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 MO2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 MO1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 MO0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Synchronous Offset 0-Asynchronous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved Reserved
Register: 0x06 (0x86)
SCSI Destination ID (SDID) Read/Write
7 R x x x x 0 0 4 3 ENC 0 0 0
R ENC[3:0]
Reserved
[7:4]
Encoded Destination SCSI ID [3:0] Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively. When executing SCRIPTS, the SCRIPTS processor writes the destination SCSI ID to this
5-18
SCSI Operating Registers
register. The SCSI ID is defined by the user in a SCRIPTS select or reselect instruction. The value written should be the binary-encoded ID value. The priority of the 16 possible IDs, in descending order, is:
Highest
7 6 5 4 3 2 1 0 15 14 13
Lowest
12 11 10 9 8
Register: 0x07 (0x87)
General Purpose (GPREG) Read/Write
7 R x x x 0 x 5 4 GPIO x x x 0
R GPIO[4:0]
Reserved
[7:5]
General Purpose [4:0] These bits can be programmed through the General Purpose Pin Control (GPCNTL) register as inputs, outputs, or to perform special functions. As an output, these pins can be used to enable or disable external terminators. It is also possible to program these signals as live inputs and sense through a SCRIPTS register to register Move Instruction. GPIO[3:0] default as inputs and GPIO4 defaults as an output pin. When configured as inputs, an internal pull-up is enabled. GPIO4 can be used to enable or disable VPP, the 12 V power supply to the external flash memory. This bit powers up with the power to the external memory disabled.
The SDMS Use of GPIO Pins SDMS software uses GPIO3 to detect a differential board. If the pin is pulled low externally, the board is configured by SDMS software as a differential board. If it is pulled high or left floating, SDMS software configures it as an SE board. The LSI Logic PCI to SCSI host adapters use the GPIO4 pin in the process of flashing a new SDMS ROM. SDMS software uses the GPIO0 pin to toggle SCSI device LEDs, turning on the LED whenever the LSI53C875 is on the SCSI bus. SDMS
5-19
software drives this pin low to turn on the LED, or drives it high to turn off the LED. SDMS software uses the GPIO[1:0] pins to support serial EEPROM access. When serial EEPROM access is enabled, GPIO1 is used as a clock and GPIO0 is used as data.
Register: 0x08 (0x88)
SCSI First Byte Received (SFBR) Read/Write
7 1B 0 0 0 0 0 0 0 0 0
This register contains the first byte received in any asynchronous information transfer phase. For example, when the LSI53C875 is operating in the initiator mode, this register contains the first byte received in the Message-In, Status, and Data-In phases. When a Block Move instruction is executed for a particular phase, the first byte received is stored in this register, even if the present phase is the same as the last phase. The first byte received or a particular input phase is not valid until after a MOVE instruction is executed. This register is also the accumulator for register read-modify-writes with the SCSI First Byte Received (SFBR) as the destination. This allows bit testing after an operation. The SCSI First Byte Received (SFBR) is not writable using the CPU, and therefore not by a Memory Move. The Load instruction may not be used to write to this register. However, it can be loaded using SCRIPTS Read/Write operations. To load the SCSI First Byte Received (SFBR) with a byte stored in system memory, the byte must first be moved to an intermediate LSI53C875 register (such as the SCRATCH register), and then to the SCSI First Byte Received (SFBR). This register also contains the state of the lower eight bits of the SCSI data bus during the selection phase if the COM bit in the DMA Control (DCNTL) register is clear.
5-20
SCSI Operating Registers
Register: 0x09 (0x89)
SCSI Output Control Latch (SOCL) Read/Write
7 REQ 0 6 ACK 0 5 BSY 0 4 SEL 0 3 ATN 0 2 MSG 0 1 C/D 0 0 I/O 0
REQ ACK BSY SEL ATN MSG C/D I/O
Assert SCSI REQ/ Signal Assert SCSI ACK/ Signal Assert SCSI BSY/ Signal Assert SCSI SEL/ Signal Assert SCSI ATN/ Signal Assert SCSI MSG/ Signal Assert SCSI C_D/ Signal Assert SCSI I_O/ Signal
7 6 5 4 3 2 1 0
This register is used primarily for diagnostic testing or programmed I/O operation. It is controlled by the SCRIPTS processor when executing SCSI SCRIPTS. SOCL is used only when transferring data using programmed I/O. Some bits are set (1) or reset (0) when executing SCSI SCRIPTS. Do not write to the register once the LSI53C875 starts executing normal SCSI SCRIPTS.
5-21
Register: 0x0A (0x09)
SCSI Selector ID (SSID) Read Only
7 VAL 0 x 6 R x x 0 0 4 3 ENID 0 0 0
VAL
SCSI Valid 7 If VAL is asserted, then the two SCSI IDs are detected on the bus during a bus-initiated selection or reselection, and the encoded destination SCSI ID bits below are valid. If VAL is deasserted, only one ID is present and the contents of the encoded destination ID are meaningless. Reserved [6:4]
R ENDID[3:0]
Encoded Destination SCSI ID [3:0] Reading the SCSI Selector ID (SSID) register immediately after the LSI53C875 is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specification. This condition is detected by examining the VAL bit above.
Register: 0x0B (0x8B)
SCSI Bus Control Lines (SBCL) Read Only
7 REQ x 6 ACK x 5 BSY x 4 SEL x 3 ATN x 2 MSG x 1 C/D x 0 I/O x
REQ ACK BSY SEL ATN
SREQ/ Status SACK/ Status SBSY/ Status SSEL/ Status SATN/ Status
7 6 5 4 3
5-22
SCSI Operating Registers
MSG C/D I/O
SMSG/ Status SC_D/ Status SI_O/ Status
2 1 0
This register returns the SCSI control line status. A bit is set when the corresponding SCSI control line is asserted. These bits are not latched; they are a true representation of what is on the SCSI bus at the time the register is read. The resulting read data is synchronized before being presented to the PCI bus to prevent parity errors from being passed to the system. This register is used for diagnostics testing or operation in low level mode.
Register: 0x0C (0x8C)
DMA Status (DSTAT) Read Only
7 DFE 1 6 MDPE 0 5 BF 0 4 ABRT 0 3 SSI 0 2 SIR 0 1 R x 0 IID 0
Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts are pending (the LSI53C875 stacks interrupts). The DIP bit in the Interrupt Status (ISTAT) register is also cleared. It is possible to mask DMA interrupt conditions individually through the DMA Interrupt Enable (DIEN) register. When performing consecutive 8-bit reads of the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One (SIST1) registers (in any order), insert a delay equivalent to 12 CLK periods between the reads to ensure that the interrupts clear properly. See Chapter 2, "Functional Description," for more information on interrupts. DFE DMA FIFO Empty 7 This status bit is set when the DMA FIFO is empty. It is possible to use it to determine if any data resides in the FIFO when an error occurs and an interrupt is generated. This bit is a pure status bit and does not cause an interrupt.
5-23
MDPE
Master Data Parity Error 6 This bit is set when the LSI53C875 as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit (bit 3 of Chip Test Four (CTEST4)). Bus Fault 5 This bit is set when a PCI bus fault condition is detected. A PCI bus fault can only occur when the LSI53C875 is bus master, and is defined as a cycle that ends with a Bad Address or Target Abort Condition. Aborted 4 This bit is set when an abort condition occurs. An abort condition occurs when a software abort command is issued by setting bit 7 of the Interrupt Status (ISTAT) register. Single Step Interrupt 3 If the Single Step Mode bit in the DMA Control (DCNTL) register is set, this bit is set and an interrupt is generated after successful execution of each SCRIPTS instruction. SCRIPTS Interrupt Instruction Received 2 This status bit is set whenever an Interrupt instruction is evaluated as true. Extended Byte Parity Error Interrupt 1 (LSI53C875N only) This bit is set whenever the LSI53C875 detects a parity error on one of the four additional parity pins on the LSI53C875N. Illegal Instruction Detected 0 This status bit is set any time an illegal or reserved instruction opcode is detected, whether the LSI53C875 is operating in single step mode or automatically executing SCSI SCRIPTS. Any of the following conditions during instruction execution also set this bit:
BF
ABRT
SSI
SIR
EBPI
IID
* The LSI53C875 is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without a disconnect occurring.
5-24
SCSI Operating Registers
* A Block Move instruction is executed with 0x000000
loaded into the DMA Byte Counter (DBC) register, indicating that there are zero bytes to move.
* During a Transfer Control instruction, the Compare
Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) register while the LSI53C875 is in target mode.
* During a Transfer Control instruction, the Carry Test
bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set.
* A Transfer Control instruction is executed with the
reserved bit 22 set.
* A Transfer Control instruction is executed with the
Wait for Valid phase bit (bit 16) set while the chip is in target mode.
* A Load/Store instruction is issued with the memory
address mapped to the operating registers of the chip, not including ROM or RAM.
* A Load/Store instruction is issued when the register
address is not aligned with the memory address.
* A Load/Store instruction is issued with bit 5 in the
DMA Command (DCMD) register cleared or bits 3 or 2 set.
* A Load/Store instruction when the count value in the
DMA Byte Counter (DBC) register is not set at 1 to 4.
* A Load/Store instruction attempts to cross a Dword
boundary.
* A Memory Move instruction is executed with one of
the reserved bits in the DMA Command (DCMD) register set.
* A Memory Move instruction is executed with the
source and destination addresses not aligned.
5-25
Register: 0x0D (0x8D)
SCSI Status Zero (SSTAT0) Read Only
7 ILF 0 6 ORF 0 5 OLF 0 4 AIP 0 3 LOA 0 2 WOA 0 1 RST 0 0 SDP0/ 0
ILF
SIDL Least Significant Byte Full 7 This bit is set when the least significant byte in the SCSI Input Data Latch (SIDL) register contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch (SIDL) register before being sent to the DMA FIFO and then to the host bus. The SCSI Input Data Latch (SIDL) register contains SCSI data received asynchronously. Synchronous data received does not flow through this register. SODR Least Significant Byte Full 6 This bit is set when the least significant byte in the SCSI Output Data Register (SODR, a hidden buffer register which is not accessible) contains data. The SODR register is used by the SCSI logic as a second storage register when sending data synchronously. It is not readable or writable by the user. It is possible to use this bit to determine how many bytes reside in the chip when an error occurs. SODL Least Significant Byte Full 5 This bit is set when the least significant byte in the SCSI Output Data Latch (SODL) contains data. The SCSI Output Data Latch (SODL) register is the interface between the DMA logic and the SCSI bus. In synchronous mode, data is transferred from the host bus to the SCSI Output Data Latch (SODL) register, and then to the SCSI Output Data Register (SODR, a hidden buffer register which is not accessible) before being sent to the SCSI bus. In asynchronous mode, data is transferred from the host bus to the SCSI Output Data Latch (SODL) register, and then to the SCSI bus. The SODR buffer register is not used for asynchronous transfers. It is possible to use this bit to determine how many bytes reside in the chip when an error occurs.
ORF
OLF
5-26
SCSI Operating Registers
AIP
Arbitration in Progress 4 Arbitration in Progress (AIP = 1) indicates that the LSI53C875 has detected a Bus Free condition, asserted BSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration 3 When set, LOA indicates that the LSI53C875 has detected a bus free condition, arbitrated for the SCSI bus, and lost arbitration due to another SCSI device asserting the SEL/ signal. Won Arbitration 2 When set, WOA indicates that the LSI53C875 has detected a Bus Free condition, arbitrated for the SCSI bus and won arbitration. The arbitration mode selected in the SCSI Control Zero (SCNTL0) register must be full arbitration and selection to set this bit. SCSI RST/ Signal 1 This bit reports the current status of the SCSI RST/ signal, and the RST signal (bit 6) in the Interrupt Status (ISTAT) register. This bit is not latched and may change as it is read. SCSI SDP0/ Parity Signal 0 This bit represents the active high current status of the SCSI SDP0/ parity signal. This signal is not latched and may change as it is read.
LOA
WOA
RST/
SDP0/
Register: 0x0E (0x8E)
SCSI Status One (SSTAT1) Read Only
7 FF[3:0] 0 0 0 0 4 3 SDP0L x 2 MSG x 1 C/D x 0 I/O x
FF[3:0]
FIFO Flags [7:4] These four bits, along with SCSI Status Two (SSTAT2), bit 4, define the number of bytes or words that currently reside in the LSI53C875's SCSI synchronous data FIFO and shown in Table 5.5. These bits are not latched and they will change as data moves through the FIFO.
5-27
Table 5.5
SCSI Synchronous Data FIFO Word Count
Bytes or Words in the SCSI FIFO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FF4 (SSTAT2 Bit 4) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
FF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
FF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
FF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
FF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
SDP0L
Latched SCSI Parity 3 This bit reflects the SCSI parity signal (SDP0/), corresponding to the data latched in the SCSI Input Data Latch (SIDL). It changes when a new byte is latched into the least significant byte of the SCSI Input Data Latch (SIDL) register. This bit is active high, in other words, it is set when the parity signal is active. SCSI MSG/ Signal SCSI C_D/ Signal 2 1
MSG C/D I/O
SCSI I_O/ Signal 0 These SCSI phase status bits are latched on the asserting edge of SREQ/ when operating in either initiator or target mode. These bits are set when the corresponding signal is active. They are useful when operating in low level mode.
5-28
SCSI Operating Registers
Register: 0x0F (0x8F)
SCSI Status Two (SSTAT2) Read Only
7 ILF1 0 6 ORF1 0 5 OLF1 0 4 FF4 0 3 SPL1 x 2 R x 1 LDSC 1 0 SDP1 x
ILF1
SIDL Most Significant Byte Full 7 This bit is set when the most significant byte in the SCSI Input Data Latch (SIDL) contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus. The SCSI Input Data Latch (SIDL) register contains SCSI data received asynchronously. Synchronous data received does not flow through this register. SODR Most Significant Byte Full 6 This bit is set when the most significant byte in the SCSI Output Data Register (SODR, a hidden buffer register which is not accessible) contains data. The SODR register is used by the SCSI logic as a second storage register when sending data synchronously. It is not accessible to the user. This bit is used to determine how many bytes reside in the chip when an error occurs. SODL Most Significant Byte Full 5 This bit is set when the most significant byte in the SCSI Output Data Latch (SODL) contains data. The SCSI Output Data Latch (SODL) register is the interface between the DMA logic and the SCSI bus. In synchronous mode, data is transferred from the host bus to the SCSI Output Data Latch (SODL) register, and then to the SCSI Output Data Register (SODR, a hidden buffer register which is not accessible) before being sent to the SCSI bus. In asynchronous mode, data is transferred from the host bus to the SCSI Output Data Latch (SODL) register, and then to the SCSI bus. The SODR buffer register is not used for asynchronous transfers. It is possible to use this bit to determine how many bytes reside in the chip when an error occurs.
ORF1
OLF1
5-29
FF4
FIFO Flags bit 4 4 This is the most significant bit in the SCSI FIFO Flags field, with the rest of the bits in SCSI Status One (SSTAT1). For a complete description of this field, see the definition for SCSI Status One (SSTAT1), bits [7:4]. Latched SCSI parity for SD[15:8] 3 This active high bit reflects the SCSI odd parity signal corresponding to the data latched into the most significant byte in the SCSI Input Data Latch (SIDL) register. Reserved 2
SPL1
R LDSC
Last Disconnect 1 This bit is used in conjunction with the Connected (CON) bit in SCSI Control One (SCNTL1). It allows the user to detect the case in which a target device disconnects, and then some SCSI device selects or reselects the LSI53C875. If the Connected bit is asserted and the LDSC bit is asserted, a disconnect is indicated. This bit is set when the Connected bit in SCSI Control One (SCNTL1) is off. This bit is cleared when a Block Move instruction is executed while the Connected bit in SCSI Control One (SCNTL1) is on. SCSI SDP1 Signal 0 This bit represents the active high current state of the SCSI SDP1 parity signal. It is unlatched and may change as it is read.
SDP1
5-30
SCSI Operating Registers
Registers: 0x10-0x13 (0x90-0x93)
Data Structure Address (DSA) Read/Write
31 DSA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DSA
Data Structure Address [31:0] This 32-bit register contains the base address used for all table indirect calculations. The Data Structure Address (DSA) register is usually loaded prior to starting an I/O, but it is possible for a SCRIPTS Memory Move to load the DSA during the I/O. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
Register: 0x14 (0x94)
Interrupt Status (ISTAT) Read/Write
7 ABRT 0 6 SRST 0 5 SIGP 0 4 SEM 0 3 CON 0 2 INTF 0 1 SIP 0 0 DIP 0
This register is accessible by the host CPU while the LSI53C875 is executing SCRIPTS (without interfering in the operation of the function). It is used to poll for interrupts if hardware interrupts are disabled. Read this register after servicing an interrupt to check for stacked interrupts. For more information on interrupt handling refer to Chapter 2, "Functional Description." ABRT Abort Operation 7 Setting this bit aborts the current operation under execution by the LSI53C875. If this bit is set and an interrupt is received, clear this bit before reading the DMA Status (DSTAT) register to prevent further aborted interrupts from being generated. The sequence to abort any operation is: 1. Set this bit.
5-31
2. 3. 4.
Wait for an interrupt. Read the Interrupt Status (ISTAT) register. If the SCSI Interrupt Pending bit is set, then read the SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1) register to determine the cause of the SCSI Interrupt and go back to Step 2. If the SCSI Interrupt Pending bit is clear, and the DMA Interrupt Pending bit is set, then write 0x00 value to this register. Read the DMA Status (DSTAT) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred.
5.
6.
SRST
Software Reset 6 Setting this bit resets the LSI53C875. All operating registers are cleared to their respective default values and all SCSI signals are deasserted. Setting this bit does not assert the SCSI RST/ signal. This reset does not clear the LSI53C700 Family Compatibility bit or any of the PCI configuration registers. This bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset also clears this bit). Signal Process 5 SIGP is a R/W bit that can be written at any time, and polled and reset using Chip Test Two (CTEST2). The SIGP bit is used in various ways to pass a flag to or from a running SCRIPTS instruction. The only SCRIPTS instruction directly affected by the SIGP bit is Wait for Selection/Reselection. Setting this bit causes that instruction to jump to the alternate address immediately. The instructions at the alternate jump address should check the status of SIGP to determine the cause of the jump. The SIGP bit is usable at any time and is not restricted to the wait for selection/reselection condition.
SIGP
SEM
Semaphore 4 The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set is while the LSI53C875 is executing a SCRIPTS operation. This bit enables the LSI53C875 to
5-32
SCSI Operating Registers
notify an external processor of a predefined condition while SCRIPTS are running. The external processor may also notify the LSI53C875 of a predefined condition and the SCRIPTS processor may take action while SCRIPTS are executing. CON Connected 3 This bit is automatically set any time the LSI53C875 is connected to the SCSI bus as an initiator or as a target. It is set after successfully completing selection or when the LSI53C875 responds to a bus-initiated selection or reselection. It is also set after the LSI53C875 wins arbitration when operating in low level mode. When this bit is clear, the LSI53C875 is not connected to the SCSI bus. Interrupt-on-the-Fly 2 This bit is asserted by an INTFLY instruction during SCRIPTS execution. SCRIPTS programs do not halt when the interrupt occurs. This bit can be used to notify a service routine, running on the main processor while the SCRIPTS processor is still executing a SCRIPTS program. If this bit is set when the Interrupt Status (ISTAT) register is read it is not automatically cleared. To clear this bit, write it to a one. The reset operation is self-clearing. If the INTF bit is set but SIP or DIP are not set, do not attempt to read the other chip status registers. An Interrupt-on-the-Fly interrupt must be cleared before servicing any other interrupts indicated by SIP or DIP. This bit must be written to one in order to clear it after it has been set. SIP SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C875. 1
INTF
The following conditions cause a SCSI interrupt to occur:
* A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
* An arbitration sequence completes * A selection or reselection time-out occurs * The LSI53C875 is selected
5-33
* The LSI53C875 is reselected * A SCSI gross error occurs * An unexpected disconnect occurs * A SCSI reset occurs * A parity error is detected * The handshake-to-handshake timer is expired * The general purpose timer is expired
To determine exactly which condition(s) caused the interrupt, read the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers. DIP DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C875. The following conditions cause a DMA interrupt to occur: 0
* A PCI parity error is detected * A bus fault is detected * An abort condition is detected * A SCRIPTS instruction is executed in single step
mode
* A SCRIPTS interrupt instruction is executed * An illegal instruction is detected
To determine exactly which condition(s) caused the interrupt, read the DMA Status (DSTAT) register.
Register: 0x18 (0x98)
Chip Test Zero (CTEST0) Read/Write
7 FMT 1 1 1 1 1 1 1 1 0
FMT
Byte Empty in DMA FIFO [7:0] This was a general purpose read/write register in previous LSI53C8XX family chips. Although it is still a read/write register, LSI Logic reserves the right to use these bits for future LSI53C8XX family enhancements.
5-34
SCSI Operating Registers
Register: 0x19 (0x99)
Chip Test One (CTEST1) Read Only
7 FMT[3:0] 1 1 1 1 0 0 4 3 FFL[3:0] 0 0 0
FMT[3:0]
Byte Empty in DMA FIFO [7:4] These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 is set. Since the FMT flags indicate the status of bytes at the bottom of the FIFO, if all FMT bits are set, the DMA FIFO is empty. Byte Full in DMA FIFO [3:0] These status bits identify the top bytes in the DMA FIFO that are full. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is full then FFL3 is set. Since the FFL flags indicate the status of bytes at the top of the FIFO, if all FFL bits are set, the DMA FIFO is full.
FFL[3:0]
Register: 0x1A (0x9A)
Chip Test Two (CTEST2) Read/Write
7 DDIR 0 6 SIGP 0 5 CIO x 4 CM x 3 SRTCH 0 2 TEOP 0 1 DREQ 0 0 DACK 1
DDIR
Data Transfer Direction 7 This status bit indicates which direction data is being transferred. When this bit is set, the data is transferred from the SCSI bus to the host bus. When this bit is clear, the data is transferred from the host bus to the SCSI bus.
5-35
SIGP
Signal Process 6 This bit is a copy of the SIGP bit in the Interrupt Status (ISTAT) register (bit 5). The SIGP bit is used to signal a running SCRIPTS instruction. When this register is read, the SIGP bit in the Interrupt Status (ISTAT) register is cleared. Configured as I/O 5 This bit is defined as the Configuration I/O Enable Status bit. This read only bit indicates if the chip is currently enabled as I/O space. Both bits 4 and 5 are set if the chip is dual-mapped. Configured as Memory 4 This bit is defined as the configuration memory enable status bit. This read only bit indicates if the chip is currently enabled as memory space. Both bits 4 and 5 are set if the chip is dual-mapped. SCRATCHA/B Operation 3 This bit controls the operation of the Scratch Register A (SCRATCHA) and Scratch Register B (SCRATCHB) registers. When it is set, SCRATCHB contains the RAM base address value from the PCI configuration RAM Base Address register. This is the base address for the 4 Kbyte internal RAM. In addition, the Scratch Register A (SCRATCHA) register displays the memory mapped based address of the chip operating registers. When this bit is cleared, the Scratch Register A (SCRATCHA) and Scratch Register B (SCRATCHB) registers return to normal operation. Bit 3 is the only writable bit in this register. All other bits are read only. When modifying this register, all other bits must be written to zero. Do not execute a read-modify-write to this register. SCSI True End of Process 2 This bit indicates the status of the LSI53C875's internal TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C875. When this bit is set, TEOP is active. When this bit is clear, TEOP is inactive.
CIO
CM
SRTCH
Note:
TEOP
5-36
SCSI Operating Registers
DREQ
Data Request Status 1 This bit indicates the status of the LSI53C875's internal Data Request signal (DREQ). When this bit is set, DREQ is active. When this bit is clear, DREQ is inactive. Data Acknowledge Status 0 This bit indicates the status of the LSI53C875's internal Data Acknowledge signal (DACK/). When this bit is set, DACK/ is inactive. When this bit is clear, DACK/ is active.
DACK
Register: 0x1B (0x9B)
Chip Test Three (CTEST3) Read/Write
7 V x x x x 4 3 FLF 0 2 CLF 0 1 FM 0 0 WRIE 0
V[3:0]
Chip revision level [7:4] These bits identify the chip revision level for software purposes. The value should be the same as the lower nibble of the PCI Revision ID register, at address 0x08 in configuration space. Flush DMA FIFO 3 When this bit is set, data residing in the DMA FIFO is transferred to memory, starting at the address in the DMA Next Address (DNAD) register. The internal DMAWR signal, controlled by the Chip Test Five (CTEST5) register, determines the direction of the transfer. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C875. Polling of FIFO flags is allowed during flush operations. Clear DMA FIFO 2 When this bit is set, all data pointers for the DMA FIFO are cleared. Any data in the FIFO is lost. After the LSI53C875 successfully clears the appropriate FIFO pointers and registers, this bit automatically clears. This bit does not clear the data visible at the bottom of the FIFO.
FLF
CLF
5-37
FM
Fetch Pin Mode 1 When set, this bit causes the FETCH/ pin to deassert during indirect and table indirect read operations. FETCH/ is only active during the opcode portion of an instruction fetch. This allows the storage of SCRIPTS in a PROM while data tables are stored in RAM. If this bit is not set, FETCH/ is asserted for all bus cycles during instruction fetches.
WRIE
Write and Invalidate Enable 0 This bit, when set, causes the issuing of Memory Write and Invalidate commands on the PCI bus whenever legal. These conditions are described in detail in Chapter 3, "PCI Functional Description."
Registers: 0x1C-0x1F (0x9C-0x9F)
Temporary (TEMP) Read/Write
31 TEMP x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
TEMP
Temporary [31:0] This 32-bit register stores the Return instruction address pointer from the Call instruction. The address pointer stored in this register is loaded into the DMA SCRIPTS Pointer (DSP) register when a Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C875 is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
5-38
SCSI Operating Registers
Register: 0x20 (0xA0)
DMA FIFO (DFIFO) Read/Write
7 BO x 0 0 0 0 0 0 0 0
BO[7:0]
Byte Offset Counter [7:0] These bits, along with bits [1:0] in the Chip Test Five (CTEST5) register, indicate the amount of data transferred between the SCSI core and the DMA core. It is used to determine the number of bytes in the DMA FIFO when an interrupt occurs. These bits are unstable while data is being transferred between the two cores. Once the chip has stopped transferring data, these bits are stable. The DMA FIFO (DFIFO) register counts the number of bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) register counts the number of bytes transferred across the host bus. The difference between these two counters represents the number of bytes remaining in the DMA FIFO. The following steps determine how many bytes are left in the DMA FIFO when an error occurs, regardless of the transfer direction: If the DMA FIFO size is set to 88 bytes: 1. Subtract the seven least significant bits of the DMA Byte Counter (DBC) register from the 7-bit value of the DMA FIFO (DFIFO) register. If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip Test Five (CTEST5) register), subtract the 10 least significant bits of the DMA Byte Counter (DBC) register from the 10-bit value of the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0] of the DMA FIFO (DFIFO) register.
2.
5-39
3.
If the DMA FIFO size is set to 88 bytes, and the result with 0x7F for a byte count between 0 and 64. If the DMA FIFO size is set to 536 bytes, and the result with 0x3FF for a byte count between 0 and 536.
Note:
To calculate the total number of bytes in both the DMA FIFO and SCSI logic, see the section on Data Paths in Chapter 2, "Functional Description."
Register: 0x21 (0xA1)
Chip Test Four (CTEST4) Read/Write
7 BDIS 0 6 ZMOD 0 5 ZSD 0 4 SRTM 0 3 MPEE 0 0 2 FBL[2:0] 0 0 0
BDIS
Burst Disable 7 When set, this bit causes the LSI53C875 to perform back-to-back cycles for all transfers. When this bit is cleared, LSI53C875 back-to-back transfers for opcode fetches and burst transfers for data moves are performed. High Impedance Mode 6 Setting this bit causes the LSI53C875 to place all output and bidirectional pins into a high impedance state. In order to read data out of the LSI53C875, clear this bit. This bit is intended for board-level testing only. Do not set this bit during normal system operation. SCSI Data High Impedance 5 Setting this bit causes the LSI53C875 to place the SCSI data bus SD[15:0] and the parity lines SDP[1:0] in a high impedance state. In order to transfer data on the SCSI bus, clear this bit. Shadow Register Test Mode 4 Setting this bit allows access to the shadow registers used by Memory-to-Memory Move operations. When this bit is set, register accesses to the Temporary (TEMP) and Data Structure Address (DSA) registers are directed to
ZMOD
ZSD
SRTM
5-40
SCSI Operating Registers
the shadow copies STEMP (Shadow TEMP) and SDSA (Shadow DSA). The registers are shadowed to prevent them from being overwritten during a Memory-to-Memory Move operation. The Data Structure Address (DSA) and Temporary (TEMP) registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respectively. This bit is intended for manufacturing diagnostics only and should not be set during normal operations. MPEE Master Parity Error Enable 3 Setting this bit enables parity checking during master data phases. A parity error during a bus master read is detected by the LSI53C875. A parity error during a bus master write is detected by the target, and the LSI53C875 is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C875 does not interrupt if a master parity error occurs. This bit is cleared at power-up. FIFO Byte Control
FBL2 0 1 1 1 1 FBL1 x 0 0 0 0 FBL0 x 0 0 1 1 DMA FIFO Byte Lane Disabled 0 1 2 3 Pins N/A D[7:0] D[15:8] D[23:16] D[31:24]
FBL[2:0]
[2:0]
These bits steer the contents of the Chip Test Six (CTEST6) register to the appropriate byte lane of the 32-bit DMA FIFO. If the FBL2 bit is set, then FBL1 and FBL0 determine which of four byte lanes can be read or written. When cleared, the byte lane read or written is determined by the current contents of the DMA Next Address (DNAD) and DMA Byte Counter (DBC) registers. Each of the four bytes that make up the 32-bit DMA FIFO is accessed by writing these bits to the proper value. For normal operation, FBL2 must equal zero.
5-41
Register: 0x22 (0xA2)
Chip Test Five (CTEST5) Read/Write
7 ADCK 0 6 BBCK 0 5 DFS 0 4 MASR 0 3 DDIR 0 2 BL2 x x 1 BO[9:8] x 0
ADCK
Clock Address Incrementor 7 Setting this bit increments the address pointer contained in the DMA Next Address (DNAD) register. The DMA Next Address (DNAD) register is incremented based on the DNAD contents and the current DBC value. This bit automatically clears itself after incrementing the DMA Next Address (DNAD) register. Clock Byte Counter 6 Setting this bit decrements the byte count contained in the 24-bit DMA Byte Counter (DBC) register. It is decremented based on the DBC contents and the current DNAD value. This bit automatically clears itself after decrementing the DMA Byte Counter (DBC) register. DMA FIFO Size 5 This bit controls the size of the DMA FIFO. When clear, the DMA FIFO appears as only 88 bytes deep. When set, the DMA FIFO size increases to 536 bytes. Using an 88-byte FIFO allows software written for other LSI53C8XX family chips to properly calculate the number of bytes residing in the chip after a target disconnect. The default value of this bit is zero. Master Control for Set or Reset Pulses 4 This bit controls the operation of bit 3. When this bit is set, bit 3 asserts the corresponding signals. When this bit is cleared, bit 3 deasserts the corresponding signals. Do not change this bit and bit 3 in the same write cycle. DMA Direction 3 Setting this bit either asserts or deasserts the internal DMA Write (DMAWR) direction signal depending on the current status of the MASR bit in this register. Asserting
BBCK
DFS
MASR
DDIR
5-42
SCSI Operating Registers
the DMAWR signal indicates that data is transferred from the SCSI bus to the host bus. Deasserting the DMAWR signal transfers data from the host bus to the SCSI bus. BL2 Burst Length 2 This bit works with bits 6 and 7 in the DMA Mode (DMODE) register to determine the burst length. For complete definitions of this field, refer to the descriptions of DMA Mode (DMODE) bits 6 and 7. This bit is disabled if an 88-byte FIFO is selected by clearing the DMA FIFO size bit. Byte Offset [1:0] These are the upper two bits of the DMA FIFO byte offset counter. The entire field is described under the DMA FIFO (DFIFO) register, bits [7:0].
BO[9:8]
Register: 0x23 (0xA3)
Chip Test Six (CTEST6) Read/Write
7 DF 0 0 0 0 0 0 0 0 0
DF[7:0]
DMA FIFO [7:0] Writing to this register writes data to the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test Four (CTEST4) register. Reading this register unloads data from the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test Four (CTEST4) register. Data written to the FIFO is loaded into the top of the FIFO. Data read out of the FIFO is taken from the bottom. To prevent DMA data from being corrupted, this register should not be accessed before starting or restarting SCRIPTS operation. Write this register only when testing the DMA FIFO using the Chip Test Four (CTEST4) register. Writes to this register while the test mode is not enabled produces unexpected results.
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Registers: 0x24-0x26 (0xA4-0xA6)
DMA Byte Counter (DBC) Read/Write
23 DBC x x x x x x x x x x x x x x x x x x x x x x x x 0
DBC
DMA Byte Counter [23:0] This 24-bit register determines the number of bytes transferred in a Block Move instruction. While sending data to the SCSI bus, the counter is decremented as data is moved into the DMA FIFO from memory. While receiving data from the SCSI bus, the counter is decremented as data is written to memory from the LSI53C875. The DBC counter is decremented each time data is transferred on the PCI bus. It is decremented by an amount equal to the number of bytes that are transferred. The maximum number of bytes that can be transferred in any one Block Move command is 16,777,215 bytes. The maximum value that can be loaded into the DMA Byte Counter (DBC) register is 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DMA Byte Counter (DBC) register, an illegal instruction interrupt occurs if the LSI53C875 is not in target mode, Command phase. The DMA Byte Counter (DBC) register is also used to hold the least significant 24 bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during table indirect I/O SCRIPTS. For a complete description, see Chapter 6, "Instruction Set of the I/O Processor." The power-up value of this register is indeterminate.
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SCSI Operating Registers
Register: 0x27 (0xA7)
DMA Command (DCMD) Read/Write
7 DCMD x x x x x x x x 0
DCMD
DMA Command [7:0] This 8-bit register determines the instruction for the LSI53C875 to execute. This register has a different format for each instruction. For complete descriptions, see Chapter 6, "Instruction Set of the I/O Processor."
Registers: 0x28-0x2B (0xA8-0xAB)
DMA Next Address (DNAD) Read/Write
31 DNAD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DNAD
DMA Next Address [31:0] This 32-bit register contains the general purpose address pointer. At the start of some SCRIPTS operations, its value is copied from the DSPS register. Its value may not be valid except in certain abort conditions. The default value of this register is zero. Do not use this register to determine data addresses during a Phase Mismatch interrupt, as its value is not always correct for this use. Use the DMA Byte Counter (DBC), DMA FIFO (DFIFO), and DMA SCRIPTS Pointer Save (DSPS) registers to calculate residual byte counts and addresses as described in Section 2.5.8.1, "Data Paths," in Chapter 2, "Functional Description."
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Registers: 0x2C-0x2F (0xAC-0xAF)
DMA SCRIPTS Pointer (DSP) Read/Write
31 DSP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DSP
DMA SCRIPTS Pointer [31:0] To execute SCSI SCRIPTS, the address of the first SCRIPTS instruction must be written to this register. In normal SCRIPTS operation, once the starting address of the SCRIPT is written to this register, SCRIPTS are automatically fetched and executed until an interrupt condition occurs. In single step mode, there is a single step interrupt after each instruction is executed. The DMA SCRIPTS Pointer (DSP) register does not need to be written with the next address, but the Start DMA bit (bit 2, DMA Control (DCNTL) register) must be set each time the step interrupt occurs to fetch and execute the next SCRIPTS command. When writing this register eight bits at a time, writing the upper eight bits begins execution of SCSI SCRIPTS. The default value of this register is zero.
Registers: 0x30-0x33 (0xB0-0xB3)
DMA SCRIPTS Pointer Save (DSPS) Read/Write
31 DSPS x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
DSPS
DMA SCRIPTS Pointer Save [31:0] This register contains the second Dword of a SCRIPTS instruction. It is overwritten each time a SCRIPTS instruction is fetched. When a SCRIPTS interrupt instruction is executed, this register holds the interrupt vector. The power-up value of this register is indeterminate.
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SCSI Operating Registers
Registers: 0x34-0x37 (0xB4-0xB7)
Scratch Register A (SCRATCHA) Read/Write
31 SCRATCHA x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
SCRATCHA
Scratch Register A [31:0] This is a general purpose, user-definable scratch pad register. Apart from CPU access, only Register Read/Write and Memory Moves into the SCRATCH register alter its contents. The LSI53C875 cannot fetch SCRIPTS instructions from this location. When bit 3 in the Chip Test Two (CTEST2) register is set, this register contains the memory-mapped base address of the operating registers. Setting Chip Test Two (CTEST2) bit 3 only causes the base address to appear in this register. Any information that was previously in the register remains intact. Any writes to this register while Chip Test Two (CTEST2), bit 3 is set passes through to the actual Scratch Register A (SCRATCHA) register. The power-up value of this register is indeterminate.
Register: 0x38 (0xB8)
DMA Mode (DMODE) Read/Write
7 BL[1:0] 0 0 6 5 SIOM 0 4 DIOM 0 3 ERL 0 2 ERMP 0 1 BOF 0 0 MAN 0
BL[1:0]
Burst Length [7:6] These bits control the maximum number of transfers performed per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. The LSI53C875 asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst size of data. Bus Request (REQ/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. The LSI53C875 inserts a "fairness delay" of four CLKs between burst length transfers (as
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set in BL[1:0]) during normal operation. The fairness delay is not inserted during PCI retry cycles. This gives the CPU and other bus master devices the opportunity to access the PCI bus between bursts.
BL2 (CTEST5 Bit 2) 0 0 0 0 1 1 1 1 Burst Length Transfers 2 4 8 16 321 641 1281 Reserved
BL1 0 0 1 1 0 0 1 1
BL0 0 1 0 1 0 1 0 1
1. Only valid if the FIFO size is set to 536 bytes.
SIOM
Source I/O-Memory Enable 5 This bit is defined as an I/O Memory Enable bit for the source address of a Memory Move or Block Move Command. If this bit is set, then the source address is in I/O space; and if cleared, then the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when the LSI53C875 is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) register are used to determine the configuration status of the LSI53C875.
DIOM
Destination I/O-Memory Enable 4 This bit is defined as an I/O Memory Enable bit for the destination address of a Memory Move or Block Move Command. If this bit is set, then the destination address is in I/O space; and if cleared, then the destination address is in memory space. This function is useful for memory- to- register operations using the Memory Move instruction when the LSI53C875 is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) register are used to determine the configuration status of the LSI53C875.
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SCSI Operating Registers
ERL
Enable Read Line 3 This bit enables a PCI Read Line command. If PCI cache mode is enabled by setting bits in the PCI Cache Line Size register, this chip issues a Read Line command on all read cycles if other conditions are met. For more information on these conditions, refer to Chapter 3, "PCI Functional Description." Enable Read Multiple 2 This bit causes Read Multiple commands to be issued on the PCI bus after certain conditions have been met. These conditions are described in Chapter 3, "PCI Functional Description." Burst Opcode Fetch Enable 1 Setting this bit causes the LSI53C875 to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership. If the instruction is a Memory-to-Memory Move type, the third Dword is accessed in a subsequent bus ownership. If the instruction is an indirect type, the additional Dword is accessed in a subsequent bus ownership. If the instruction is a table indirect block move type, the chip accesses the remaining two Dwords in a subsequent bus ownership, thereby fetching the four Dwords required in two bursts of two Dwords each. This bit has no effect if SCRIPTS instruction prefetching is enabled. Manual Start Mode 0 Setting this bit prevents the LSI53C875 from automatically fetching and executing SCSI SCRIPTS when the DMA SCRIPTS Pointer (DSP) register is written. When this bit is set, the Start DMA bit in the DMA Control (DCNTL) register must be set to begin SCRIPTS execution. Clearing this bit causes the LSI53C875 to automatically begin fetching and executing SCSI SCRIPTS when the DMA SCRIPTS Pointer (DSP) register is written. This bit normally is not used for SCSI SCRIPTS operations.
ERMP
BOF
MAN
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Register: 0x39 (0xB9)
DMA Interrupt Enable (DIEN) Read/Write
7 R x 6 MDPE 0 5 BF 0 4 ABRT 0 3 SSI 0 2 SIR 0 1 R x 0 IID 0
R MDPE BF ABRT SSI SIR EBPE IID
Reserved Master Data Parity Error Bus Fault Aborted Single-step Interrupt SCRIPTS Interrupt Instruction Received Extended Byte Parity Enable (LSI53C875N only) Illegal Instruction Detected
7 6 5 4 3 2 1 0
This register contains the interrupt mask bits corresponding to the interrupting conditions described in the DMA Status (DSTAT) register. An interrupt is masked by clearing the appropriate mask bit. Masking an interrupt prevents IRQ/ from being asserted for the corresponding interrupt, but the status bit is still set in the DMA Status (DSTAT) register. Masking an interrupt does not prevent the ISTAT DIP from being set. All DMA interrupts are considered fatal, therefore SCRIPTS stops running when this condition occurs, whether or not the interrupt is masked. Setting a mask bit enables the assertion of IRQ/ for the corresponding interrupt. (A masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the ISTAT SIP or DIP bit is set.) The IRQ/ output is latched. Once asserted, it will remain asserted until the interrupt is cleared by reading the appropriate status register. Masking an interrupt after the IRQ/ output is asserted does not cause deassertion of IRQ/.
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SCSI Operating Registers
For more information on interrupts, see Chapter 2, "Functional Description."
Register: 0x3A (0xBA)
Scratch Byte Register (SBR) Read/Write This is a general purpose register. Apart from CPU access, only register Read/Write and Memory Moves into this register will alter its contents. The default value of this register is zero. This register was called the DMA Watchdog Timer on previous LSI53C8XX family products.
Register: 0x3B (0xBB)
DMA Control (DCNTL) Read/Write
7 CLSE 0 6 PFF 0 5 PFEN 0 4 SSM 0 3 IRQM 0 2 STD 0 1 IRQD 0 0 COM 0
CLSE
Cache Line Size Enable 7 Setting this bit enables the LSI53C875 to sense and react to cache line boundaries set up by the DMODE or PCI Cache Line Size register, whichever contains the smaller value. Clearing this bit disables the cache line size logic and the LSI53C875 monitors the cache line size using the DMA Mode (DMODE) register. Prefetch Flush Setting this bit causes the prefetch unit to flush its contents. The bit clears after the flush is complete. 6
PFF
PFEN
Prefetch Enable 5 Setting this bit enables the prefetch unit if the burst size is equal to or greater than four. For more information on SCRIPTS instruction prefetching, see Chapter 2, "Functional Description." Single Step Mode 4 Setting this bit causes the LSI53C875 to stop after executing each SCRIPTS instruction, and generates a single step interrupt. When this bit is cleared, the LSI53C875 does not stop after each instruction. It
SSM
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continues fetching and executing instructions until an interrupt condition occurs. For normal SCSI SCRIPTS operation, keep this bit clear. To restart the LSI53C875 after it generates a SCRIPTS Step interrupt, read the Interrupt Status (ISTAT) and DMA Status (DSTAT) registers to recognize and clear the interrupt. Then set the START DMA bit in this register. IRQM IRQ Mode 3 When set, this bit will enable a totem pole driver for the IRQ pin. When cleared, this bit enables an open drain driver for the IRQ pin with a internal weak pull-up. This bit is reset at power up. The bit should remain cleared to retain full PCI compliance. Start DMA Operation 2 The LSI53C875 fetches a SCSI SCRIPTS instruction from the address contained in the DMA SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C875 is in one of the following modes:
STD
* Manual start mode - Bit 0 in the DMA Mode
(DMODE) register is set
* Single step mode - Bit 4 in the DMA Control (DCNTL)
register is set When the LSI53C875 is executing SCRIPTS in manual start mode, the Start DMA bit must to be set to start instruction fetches, but need not be set again until an interrupt occurs. When the LSI53C875 is in single step mode, the Start DMA bit needs to be set to restart execution of SCRIPTS after a single step interrupt. IRQD IRQ Disable 1 Setting this bit disables the IRQ pin. Clearing the bit enables normal operation. As with any other register other than ISTAT, this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution. For more information on the use of this bit in interrupt handling, see Chapter 2, "Functional Description."
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SCSI Operating Registers
COM
LSI53C700 Family Compatibility 0 When the COM bit is cleared, the LSI53C875 behaves in a manner compatible with the LSI53C700 family; selection/reselection IDs are stored in both the SCSI Selector ID (SSID) and SCSI First Byte Received (SFBR) registers. When this bit is set, the ID is stored only in the SCSI Selector ID (SSID) register, protecting the SFBR from being overwritten if a selection/reselection occurs during a DMA register-to-register operation. This bit is not affected by a software reset.
Register: 0x3C-0x3F (0xBC-0xBF)
Adder Sum Output (ADDER) Read Only
31 ADDER x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
ADDER
Adder Sum Output [31:0] This register contains the output of the internal adder, and is used primarily for test purposes. The power-up value for this register is indeterminate.
Register: 0x40 (0xC0)
SCSI Interrupt Enable Zero (SIEN0) Read/Write
7 M/A 0 6 CMP 0 5 SEL 0 4 RSL 0 3 SGE 0 2 UDC 0 1 RST 0 0 PAR 0
This register contains the interrupt mask bits corresponding to the interrupting conditions described in the SCSI Interrupt Status Zero (SIST0) register. An interrupt is masked by clearing the appropriate mask bit. For more information on interrupts, see Chapter 2, "Functional Description."
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M/A
SCSI Phase Mismatch - Initiator Mode; 7 SCSI ATN Condition - Target Mode In initiator mode, this bit is set when the SCSI phase asserted by the target and sampled during SREQ/ does not match the expected phase in the SCSI Output Control Latch (SOCL) register. This expected phase is automatically written by SCSI SCRIPTS. In target mode, this bit is set when the initiator has asserted SATN/. See the Disable Halt on Parity Error or SATN/ Condition bit in the SCSI Control One (SCNTL1) register for more information on when this status is actually raised. Function Complete Full arbitration and selection sequence is completed. 6
CMP SEL
Selected 5 Indicates the LSI53C875 is selected by a SCSI target device. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur. Reselected 4 Indicates the LSI53C875 is reselected by a SCSI initiator device. Set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register for this to occur. SCSI Gross Error The following conditions are considered SCSI Gross Errors: 3
RSL
SGE
* Data underflow - reading the SCSI FIFO when no
data is present.
* Data overflow - writing to the SCSI FIFO while it is
full.
* Offset underflow - receiving an SACK/ pulse in target
mode before the corresponding SREQ/ is set.
* Offset overflow - receiving an SREQ/ pulse in the
initiator mode, and exceeding the maximum offset (defined by the MO[3:0] bits in the SCSI Transfer (SXFER) register).
* A phase change in the initiator mode, with an
outstanding SREQ/SACK/ offset.
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SCSI Operating Registers
* Residual data in SCSI FIFO - starting a transfer other
than synchronous data receive with data left in the SCSI synchronous receive FIFO. UDC Unexpected Disconnect 2 This condition only occurs in the initiator mode. It happens when the target to which the LSI53C875 is connected disconnects from the SCSI bus unexpectedly. See the SCSI Disconnect Unexpected bit in the SCSI Control Two (SCNTL2) register for more information on expected versus unexpected disconnects. Any disconnect in low level mode causes this condition. SCSI Reset Condition 1 Indicates assertion of the SRST/ signal by the LSI53C875 or any other SCSI device. This condition is edgetriggered, so multiple interrupts cannot occur because of a single SRST/ pulse. SCSI Parity Error 0 Indicates detection of a parity error while receiving or sending SCSI data. See the Disable Halt on Parity Error or SATN/ Condition bits in the SCSI Control One (SCNTL1) register for more information on when this condition is actually raised.
RST
PAR
Register: 0x41 (0xC1)
SCSI Interrupt Enable One (SIEN1) Read/Write
7 R x x x x x 3 2 STO 0 1 GEN 0 0 HTH 0
This register contains the interrupt mask bits corresponding to the interrupting conditions described in the SCSI Interrupt Status One (SIST1) register. An interrupt is masked by clearing the appropriate mask bit. For more information on interrupts, refer to Chapter 2, "Functional Description."
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R STO
Reserved
[7:3]
Selection or Reselection Time-out 2 The SCSI device which the LSI53C875 is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register bits [3:0] for more information on the time-out timer. General Purpose Timer Expired 1 The general purpose timer is expired. The time measured is the time between enabling and disabling of the timer. See the description of the SCSI Timer One (STIME1) register, bits [3:0], for more information on the general purpose timer. Handshake-to-Handshake Timer Expired 0 The handshake-to-handshake timer is expired. The time measured is the SCSI Request-to-Request (target) or Acknowledge-to-Acknowledge (initiator) period. See the description of the SCSI Timer Zero (STIME0) register, bits [7:4], for more information on the handshake-tohandshake timer.
GEN
HTH
Register: 0x42 (0xC2)
SCSI Interrupt Status Zero (SIST0) Read Only
7 M/A 0 6 CMP 0 5 SEL 0 4 RSL 0 3 SGE 0 2 UDC 0 1 RST 0 0 PAR 0
Reading the SCSI Interrupt Status Zero (SIST0) register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable Zero (SIEN0) register or not. Each bit set indicates occurrence of the corresponding condition. Reading the SIST0 clears the interrupt status. Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C875 stacks interrupts). SCSI interrupt conditions are individually masked through the SCSI Interrupt Enable Zero (SIEN0) register.
5-56
SCSI Operating Registers
When performing consecutive 8-bit reads of the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One (SIST1) registers (in any order), insert a delay equivalent to 12 CLK periods between the reads to ensure the interrupts clear properly. Also, if reading the registers when both the ISTAT SIP and DIP bits may not be set, read the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers before the DMA Status (DSTAT) register to avoid missing a SCSI interrupt. For more information on interrupts, refer to Chapter 2, "Functional Description." M/A Initiator Mode: Phase Mismatch; 7 Target Mode: SATN/ Active In initiator mode, this bit is set if the SCSI phase asserted by the target does not match the instruction. The phase is sampled when SREQ/ is asserted by the target. In target mode, this bit is set when the SATN/ signal is asserted by the initiator. Function Complete 6 This bit is set when an arbitration only or full arbitration sequence is completed. Selected 5 This bit is set when the LSI53C875 is selected by another SCSI device. The Enable Response to Selection bit must be set in the SCSI Chip ID (SCID) register (and the RESPID register must hold the chip's ID) for the LSI53C875 to respond to selection attempts. Reselected 4 This bit is set when the LSI53C875 is reselected by another SCSI device. The Enable Response to Reselection bit must be set in the SCSI Chip ID (SCID) register (and the RESPID register must hold the chip's ID) for the LSI53C875 to respond to reselection attempts. SCSI Gross Error 3 This bit is set when the LSI53C875 encounters a SCSI Gross Error Condition. The following conditions can result in a SCSI Gross Error Condition:
CMP
SEL
RSL
SGE
* Data Underflow - reading the SCSI FIFO when no
data is present.
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* Data Overflow - writing too many bytes to the SCSI
FIFO, or the synchronous offset causes overwriting the SCSI FIFO.
* Offset Underflow - the LSI53C875 is operating in
target mode and a SACK/ pulse is received when the outstanding offset is zero.
* Offset Overflow - the other SCSI device sends a
SREQ/ or SACK/ pulse with data which exceeds the maximum synchronous offset defined by the SCSI Transfer (SXFER) register.
* A phase change occurs with an outstanding
synchronous offset when the LSI53C875 is operating as an initiator.
* Residual data in the synchronous data FIFO - a
transfer other than synchronous data receive is started with data left in the synchronous data FIFO. UDC Unexpected Disconnect 2 This bit is set when the LSI53C875 is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C875 operates in the initiator mode. When the LSI53C875 operates in low level mode, any disconnect causes an interrupt, even a valid SCSI disconnect. This bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the STO interrupt, since this is not considered an expected disconnect). SCSI RST/ Received 1 This bit is set when the LSI53C875 detects an active SRST/ signal, whether the reset is generated external to the chip or caused by the Assert SRST/ bit in the SCSI Control One (SCNTL1) register. The SCSI reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the SRST/ signal. Parity Error 0 This bit is set when the LSI53C875 detects a parity error while receiving SCSI data. The Enable Parity Checking bit (bit 3 in the SCSI Control Zero (SCNTL0) register) must be set for this bit to become active. The LSI53C875 always generates parity when sending SCSI data.
RST
PAR
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SCSI Operating Registers
Register: 0x43 (0xC3)
SCSI Interrupt Status One (SIST1) Read Only
7 R x x x x x 3 2 STO 0 1 GEN 0 0 HTH 0
Reading the SCSI Interrupt Status One (SIST1) register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable One (SIEN1) register or not. Each bit that is set indicates an occurrence of the corresponding condition. Reading the SCSI Interrupt Status One (SIST1) clears the interrupt condition. R STO Reserved [7:3]
Selection or Reselection Time-out 2 The SCSI device which the LSI53C875 is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer. General Purpose Timer Expired 1 This bit is set when the general purpose timer expires. The time measured is the time between enabling and disabling of the timer. See the description of the SCSI Timer One (STIME1) register, bits [3:0], for more information on the general purpose timer. Handshake-to-Handshake Timer Expired 0 This bit is set when the handshake-to-handshake timer expires. The time measured is the SCSI Request-toRequest (target) or Acknowledge-to-Acknowledge (initiator) period. See the description of the SCSI Timer Zero (STIME0) register, bits [7:4], for more information on the handshake-to-handshake timer.
GEN
HTH
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Register: 0x44 (0xC4)
SCSI Longitudinal Parity (SLPAR) Read/Write
7 SLPAR x x x x x x x x 0
SLPAR
SCSI Longitudinal Parity [7:0] The SCSI Longitudinal Parity (SLPAR) register consists of two multiplexed bytes; other register bit settings determine what is displayed at this memory location at any given time. When bit 5 in the SCSI Control Two (SCNTL2) (SLPMD) register is cleared, the chip XORs the high and low bytes of the SCSI Longitudinal Parity (SLPAR) register together to give a single byte value which is displayed in the SCSI Longitudinal Parity (SLPAR) register. If the SLPMD bit is set, then the SCSI Longitudinal Parity (SLPAR) register shows either the high byte or the low byte of the SLPAR word. The SLPAR High Byte Enable bit, SCSI Control Two (SCNTL2) bit 4, determines which byte of the SCSI Longitudinal Parity (SLPAR) register is visible on the SCSI Longitudinal Parity (SLPAR) register at any given time. If this bit is cleared, the SCSI Longitudinal Parity (SLPAR) register contains the low byte of the SLPAR word; if it is set, the SCSI Longitudinal Parity (SLPAR) register contains the high byte of the SLPAR word. This register performs a bytewise longitudinal parity check on all SCSI data received or sent through the SCSI core. If one of the bytes received or sent (usually the last) is the set of correct even parity bits, SCSI Longitudinal Parity (SLPAR) should go to zero (assuming it started at zero). As an example, suppose that the following three data bytes and one check byte are received from the SCSI bus (all signals are shown active HIGH):
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SCSI Operating Registers
Data Bytes - 1. 11001100 2. 01010101 3. 00001111 4. 10010110
Running SLPAR 00000000 11001100 (XOR of word 1) 10011001 (XOR of word 1 and 2) 10010110 (XOR of word 1, 2 and 3) Even Parity 00000000
A one in any bit position of the final SLPAR value would indicate a transmission error. The SCSI Longitudinal Parity (SLPAR) register is also used to generate the check bytes for SCSI send operations. If the SCSI Longitudinal Parity (SLPAR) register contains all zeros prior to sending a block move, it contains the appropriate check byte at the end of the block move. This byte must then be sent across the SCSI bus. Note: Writing any value to this register resets it to zero.
The longitudinal parity checks are meant to provide an added measure of SCSI data integrity and are entirely optional. This register does not latch SCSI selection/reselection IDs under any circumstances. The default value of this register is zero.
Register: 0x45 (0xC5)
SCSI Wide Residue (SWIDE) Read/Write
7 SWIDE x x x x x x x x 0
SWIDE
SCSI Wide Residue [7:0] After a wide SCSI data receive operation, this register contains a residual data byte if the last byte received was never sent across the DMA bus. It represents either the first data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an Ignore
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Wide Residue message is received. It may also be an overrun data byte. The power-up value of this register is indeterminate.
Register: 0x46 (0xC6)
Memory Access Control (MACNTL) Read/Write
7 TYP 1 1 1 1 4 3 DWR 0 2 DRD 0 1 PSCPT 0 0 SCPTS 0
TYP[3:0]
Chip Type [7:4] These bits identify the chip type for software purposes. This technical manual applies to devices that have these bits set to 0x07. Bits 3 through 0 of this register are used to determine if an external bus master access is to local or far memory. When bits 3 through 0 are set, the corresponding access is considered local and the MAC/_TESTOUT pin is driven high. When these bits are clear, the corresponding access is to far memory and the MAC/_TESTOUT pin is driven low. This function is enabled after a Transfer Control SCRIPTS instruction is executed.
DWR
DataWR 3 This bit is used to define if a data write is considered to be a local memory access. DataRD 2 This bit is used to define if a data read is considered to be a local memory access. Pointer SCRIPTS 1 This bit is used to define if a pointer to a SCRIPTS indirect or table indirect fetch is considered to be a local memory access. SCRIPTS This bit is used to define if a SCRIPTS fetch is considered to be a local memory access. 0
DRD
PSCPT
SCPTS
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SCSI Operating Registers
Register: 0x47 (0xC7)
General Purpose Pin Control (GPCNTL) Read/Write
7 ME 0 6 FE 0 5 R x 0 4 GPIO 1 1 1 2 1 GPIO 1 0
This register is used to determine if the pins controlled by the General Purpose (GPREG) register are inputs or outputs. Bits [4:0] in GPCNTL correspond to bits [4:0] in the General Purpose (GPREG) register. When the bits are enabled as inputs, an internal pull-up is also enabled. ME Master Enable 7 The internal bus master signal is presented on GPIO1 if this bit is set, regardless of the state of bit 1 (GPIO1_EN). Fetch Enable 6 The internal opcode fetch signal is presented on GPIO0 if this bit is set, regardless of the state of bit 0 (GPIO0_EN). Reserved 5
FE
R
GPIO4_EN[4:2] GPIO Enable [4:2] The General purpose control, corresponding to bits [4:2] in the General Purpose (GPREG) register and pins 60, 59, and 57. GPIO4 powers up as a general purpose output, and GPIO[3:2] power-up as general purpose inputs. GPIO1_EN[1:0] GPIO Enable [1:0] These bits power-up set, causing the GPIO1 and GPIO0 pins to become inputs. Clearing these bits causes GPIO[1:0] to become outputs.
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Register: 0x48 (0xC8)
SCSI Timer Zero (STIME0) Read/Write
7 HTH[3:0] 0 0 0 0 0 0 4 3 SEL[3:0] 0 0 0
HTH
Handshake-to-Handshake Timer Period [7:4] These bits select the handshake-to-handshake time-out period, the maximum time between SCSI handshakes (SREQ/ to SREQ/ in target mode, or SACK/ to SACK/ in initiator mode). When this timing is exceeded, an interrupt is generated and the HTH bit in the SCSI Interrupt Status One (SIST1) register is set. The following table contains time-out periods for the Handshake-to-Handshake Timer, the Selection/Reselection Timer (bits [3:0]), and the General Purpose Timer (SCSI Timer One (STIME1), bits [3:0]. For a more detailed explanation of interrupts, refer to Chapter 2, "Functional Description."
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SCSI Operating Registers
HTH [7:4] SEL [3:0] GEN [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Minimum Time-out1 40 MHz/80 MHz Disabled 125 s 250 s 500 s 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1.024 s 2.048 s 50 MHz Disabled 100 s 200 s 400 s 800 s 1.6 ms 3.2 ms 6.4 ms 12.8 ms 25.6 ms 51.2 ms 102.4 ms 204.8 ms 409.6 ms 819.2 ms 1.6384 s
1. These values will be correct if the CCF bits in the SCSI Control Three (SCNTL3) register are set according to the valid combinations in the bit description.
SEL
Selection Time-Out [3:0] These bits select the SCSI selection/reselection time-out period. When this timing (plus the 200 s selection abort time) is exceeded, the STO bit in the SCSI Interrupt Status One (SIST1) register is set. For a more detailed explanation of interrupts, refer to Chapter 2, "Functional Description."
5-65
Register: 0x49 (0xC9)
SCSI Timer One (STIME1) Read/Write
7 R x 6 HTHBA 0 5 GENSF 0 4 HTHSF 0 0 0 3 GEN[3:0] 0 0 0
R HTHBA
Reserved
7
Handshake-to-Handshake Timer Bus 6 Activity Enable Setting this bit causes this timer to begin testing for SCSI REQ/ACK activity as soon as SBSY/ is asserted, regardless of the agents participating in the transfer. General Purpose Timer Scale Factor 5 Setting this bit causes this timer to shift by a factor of 16.
GENSF
5-66
SCSI Operating Registers
HTH [7:4] SEL [3:0] GEN [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Minimum Time-out1 (50 MHz Clock) GENSF = 0 Disabled 100 s 200 s 400 s 800 s 1.6 ms 3.2 ms 6.4 ms 12.8 ms 25.6 ms 51.2 ms 102.4 ms 204.8 ms 409.6 ms 819.2 ms 1.6 s GENSF = 1 Disabled 1.6 ms 3.2 ms 6.4 ms 12.8 ms 25.6 ms 51.2 ms 102.4 ms 204.8 ms 409.6 ms 819.2 ms 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s
1. These values will be correct if the CCF bits in the SCSI Control Three (SCNTL3) register are set according to the valid combinations in the bit description.
5-67
HTH [7:4] SEL [3:0] GEN [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Minimum Time-out1 (80 MHz Clock) GENSF = 0 Disabled 125 s 250 s 500 s 1 s 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1.024 s 2.048 s GENSF = 1 Disabled 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1s 2s 4.1 s 8.2 s 16.4 s 32.8 s
1. These values will be correct if the CCF bits in the SCSI Control Three (SCNTL3) register are set according to the valid combinations in the bit description.
HTHSF GEN[3:0]
Handshake-to-Handshake Timer Scale Factor 4 Setting this bit causes this timer to shift by a factor of 16. General Purpose Timer Period [3:0] These bits select the period of the general purpose timer. The time measured is the time between enabling and disabling of the timer. When this timing is exceeded, the
5-68
SCSI Operating Registers
GEN bit in the SCSI Interrupt Status One (SIST1) register is set. Refer to the table under SCSI Timer Zero (STIME0), bits [3:0], for the available time-out periods. Note: To reset a timer before it expires and obtain repeatable delays, the time value must be written to zero first, and then written back to the desired value. This is also required when changing from one time value to another. See Chapter 2, "Functional Description," for an explanation of how interrupts are generated when the timers expire.
Register: 0x4A (0xCA)
Response ID Zero (RESPID0) Read/Write
7 ID x x x x x x x x 0
RESPID0
Response ID Zero [7:0] RESPID0 and RESPID1 contain the selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus. Each bit represents one possible ID with the most significant bit of RESPID1 representing ID 15 and the least significant bit of RESPID0 representing ID 0. The SCSI Chip ID (SCID) register still contains the chip ID used during arbitration. The chip can respond to more than one ID because more than one bit can be set in the Response ID One (RESPID1) and Response ID Zero (RESPID0) registers. However, the chip can arbitrate with only one ID value in the SCSI Chip ID (SCID) register.
5-69
Register: 0x4B (0xCB)
Response ID One (RESPID1) Read/Write
15 ID x x x x x x x x 8
RESPID1
Response ID One [15:8] RESPID0 and RESPID1 contain the selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus. Each bit represents one possible ID with the most significant bit of RESPID1 representing ID 15 and the least significant bit of RESPID0 representing ID 0. The SCSI Chip ID (SCID) register still contains the chip ID used during arbitration. The chip can respond to more than one ID because more than one bit can be set in the Response ID One (RESPID1) and Response ID Zero (RESPID0) registers. However, the chip can arbitrate with only one ID value in the SCSI Chip ID (SCID) register.
Register: 0x4C (0xCC)
SCSI Test Zero (STEST0) Read Only
7 SSAID 0 0 0 0 4 3 SLT 0 2 ART x 1 SOZ 1 0 SOM 1
SSAID
SCSI Selected As ID [7:4] These bits contain the encoded value of the SCSI ID that the LSI53C875 is selected or reselected as during a SCSI selection or reselection phase. These bits are read only and contain the encoded value of 0-15 possible IDs that are used to select the LSI53C875. During a SCSI selection or reselection phase, when a valid ID has been put on the bus, and the LSI53C875 responds to that ID, the "selected as" ID is written into these bits. These bits are used with the RESPID registers to allow response to multiple IDs on the bus.
5-70
SCSI Operating Registers
SLT
Selection Response Logic Test 3 This bit is set when the LSI53C875 is ready to be selected or reselected. This does not take into account the bus settle delay of 400 ns. This bit is used for functional test and fault purposes. Arbitration Priority Encoder Test 2 This bit is always set when the LSI53C875 exhibits the highest priority ID asserted on the SCSI bus during arbitration. It is primarily used for chip level testing, but it may be used during low level mode operation to determine if the LSI53C875 has won arbitration. SCSI Synchronous Offset Zero 1 This bit indicates that the current synchronous SREQ/SACK offset is zero. This bit is not latched and may change at any time. It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C875, functioning as an initiator, is waiting for the target to request data transfers. If the LSI53C875 is a target, then the initiator has sent the offset number of acknowledges. SCSI Synchronous Offset Maximum 0 This bit indicates that the current synchronous SREQ/SACK offset is the maximum specified by bits [3:0] in the SCSI Transfer (SXFER) register. This bit is not latched and may change at any time. It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C875, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C875 is an initiator, then the target has sent the offset number of requests.
ART
SOZ
SOM
5-71
Register: 0x4D (0xCD)
SCSI Test One (STEST1) Read/Write
7 SCLK 0 6 SISO 0 x 5 R x 4 3 DBLEN 0 2 DBLSEL 0 x 1 R x 0
SCLK
SCSI Clock 7 When set, this bit disables the external SCLK (SCSI Clock) pin, and the chip uses the PCI clock as the internal SCSI clock. If a transfer rate of 10 Mbytes/s (or 20 Mbytes/s on a wide SCSI bus) is desired on the SCSI bus, this bit must be cleared and a 40 MHz external SCLK must be provided. SCSI Isolation Mode 6 This bit allows the LSI53C875 to put the SCSI bidirectional and input pins into a low power mode when the SCSI bus is not in use. When this bit is set, the SCSI bus inputs are logically isolated from the SCSI bus. Reserved [5:4]
SISO
R DBLEN
Doubler Enable 3 Set this bit to bring the SCSI clock doubler out of the powered-down state. The default value of this bit is clear (SCSI clock doubler powered down). Set bit 2 after setting this bit, to double the SCLK frequency. Doubler Select 2 Set this bit after powering up the SCSI clock doubler to double the SCLK frequency. This bit has no effect unless bit 3 is set. Reserved [1:0]
DBLSEL
R
5.0.0.1 Doubling the SCSI CLK Frequency The LSI53C875 SCSI clock doubler doubles a 40 MHz SCSI clock, increasing the frequency to 80 MHz. Follow these steps to use the clock doubler: 1. Set the SCLK Doubler Enable bit (SCSI Test One (STEST1), bit 3).
5-72
SCSI Operating Registers
2. Wait 20 s. 3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test Three (STEST3), bit 5). 4. Set the clock conversion factor using the SCF and CCF fields in the SCSI Control Three (SCNTL3) register. 5. Set the SCLK Doubler Select bit (SCSI Test One (STEST1), bit 2). 6. Clear the Halt SCSI Clock bit.
Register: 0x4E (0xCE)
SCSI Test Two (STEST2) Read/Write
7 SCE 0 6 ROF 0 5 DIF 0 4 SLB 0 3 SZM 0 2 AWS 0 1 EXT 0 0 LOW 0
SCE
SCSI Control Enable 7 Setting this bit allows all SCSI control and data lines to be asserted through the SOCL and SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C875 is configured as a target or initiator. Note: Do not set this bit during normal operation, since it could cause contention on the SCSI bus. It is included for diagnostic purposes only. Reset SCSI Offset 6 Setting this bit clears any outstanding synchronous SREQ/SACK offset. Set this bit if a SCSI gross error condition occurs and to clear the offset when a synchronous transfer does not complete successfully. The bit automatically clears itself after resetting the synchronous offset. SCSI Differential Mode 5 Setting this bit allows the LSI53C875 to interface properly to external differential transceivers. Its only real effect is to 3-state the SBSY/, SSEL/, and SRST/ pads so that they can be used as pure inputs. Clearing this bit enables SE operation. Set this bit in the initialization routine if the differential pair interface is used.
ROF
DIF
5-73
SLB
SCSI Loopback Mode 4 Setting this bit allows the LSI53C875 to perform SCSI loopback diagnostics. That is, it enables the SCSI core to simultaneously perform as both the initiator and the target. SCSI High Impedance Mode 3 Setting this bit places all the open drain 48 mA SCSI drivers into a high impedance state. This is to allow internal loopback mode operation without affecting the SCSI bus. Always Wide SCSI 2 When this bit is set, all SCSI information transfers are done in 16-bit wide mode. This includes data, message, command, status, and reserved phases. Normally, deassert this bit since 16-bit wide message, command, and status phases are not supported by the SCSI specifications. Extend SREQ/SACK Filtering 1 TolerANT SCSI receiver technology includes a special digital filter on the SREQ/ and SACK/ pins which causes the disregarding of glitches on deasserting edges. Setting this bit increases the filtering period from 30 ns to 60 ns on the deasserting edge of the SREQ/ and SACK/ signals. Never set this bit during fast SCSI (greater than 5 Mbytes transfers per second) operations, because a valid assertion could be treated as a glitch. This bit does not affect the filtering period when the Ultra Enable bit in the SCSI Control Three (SCNTL3) register is set. When the LSI53C875 is executing Ultra SCSI transfers, the filtering period is automatically set at 15 ns. SCSI Low level Mode 0 Setting this bit places the LSI53C875 in low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may be performed by setting the start sequence bit as described in the SCSI Control Zero (SCNTL0) register. SCSI bus transfers are performed by manually asserting and polling SCSI signals. Clearing this bit allows instructions to be executed in SCSI SCRIPTS mode. It is not necessary to
SZM
AWS
EXT
LOW
5-74
SCSI Operating Registers
set this bit for access to the SCSI bit-level registers SCSI Output Data Latch (SODL), SCSI Bus Control Lines (SBCL), and input registers.
Register: 0x4F (0xCF)
SCSI Test Three (STEST3) Read/Write
7 TE 0 6 STR 0 5 HSC 0 4 DSI 0 3 S16 0 2 TTM 0 1 CSF 0 0 STW 0
TE
TolerANT Enable 7 Setting this bit enables the active negation portion of TolerANT technology. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively deasserted, instead of relying on external pull-ups, when the LSI53C875 is driving these signals. Active deassertion of these signals occurs only when the LSI53C875 is in an information transfer phase. When operating in a differential environment or at fast SCSI timings, TolerANT Active negation should be enabled to improve setup and deassertion times. Active negation is disabled after reset or when this bit is cleared. For more information on TolerANT technology, refer to Chapter 1, "General Description." Set this bit if the ULTRA bit in SCSI Control Three (SCNTL3) is set. SCSI FIFO Test Read 6 Setting this bit places the SCSI core into a test mode in which the SCSI FIFO is easily read. Reading the least significant byte of the SCSI Output Data Latch (SODL) register causes the FIFO to unload. The functions are summarized in the table below.
Register Name SODL SODL0 SODL1 Register Operation Read Read Read FIFO Function Unload Unload None
STR
FIFO Bits [15:0] [7:0] [15:8]
5-75
HSC
Halt SCSI Clock 5 Asserting this bit causes the internal divided SCSI clock to come to a stop in a glitchless manner. This bit is used for test purposes or to lower IDD during a power-down mode. This bit is used when the SCSI clock doubler is operating. For additional information on the clock doubler, see Chapter 2, "Functional Description."
DSI
Disable Single Initiator Response 4 If this bit is set, the LSI53C875 ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C875 while this bit is set, the LSI53C875's SCSI ID and the initiator's SCSI ID must both be asserted. Assert this bit in SCSI-2 systems so that a single bit error on the SCSI bus is not interpreted as a single initiator response. 16-Bit System 3 If this bit is set, all devices in the SCSI system implementation are assumed to be 16-bit. This causes the LSI53C875 to always check the parity bit for SCSI IDs [15:8] during bus-initiated selection or reselection, assuming parity checking has been enabled. If an 8-bit SCSI device attempts to select the LSI53C875 while this bit is set, the LSI53C875 will ignore the selection attempt. This is because the parity bit for IDs [15:8] will be undriven. See the description of the Enable Parity Checking bit in the SCSI Control Zero (SCNTL0) register for more information. Timer Test Mode 2 Asserting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing all three time-out periods. Setting this bit starts all three timers and if the respective bits in the SCSI Interrupt Enable One (SIEN1) register are asserted, the LSI53C875 generates interrupts at time-out. This bit is intended for internal manufacturing diagnosis and should not be used. Clear SCSI FIFO 1 Setting this bit causes the "full flags" for the SCSI FIFO to be cleared. This empties the FIFO. This bit is self-clearing. In addition to the SCSI FIFO pointers, the
S16
TTM
CSF
5-76
SCSI Operating Registers
SCSI Input Data Latch (SIDL), SCSI Output Data Latch (SODL), and SODR full bits in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) are cleared. STW SCSI FIFO Test Write 0 Setting this bit places the SCSI core into a test mode in which the FIFO is easily read or written. While this bit is set, writes to the least significant byte of the SCSI Output Data Latch (SODL) register cause the entire word contained in this register to be loaded into the FIFO. Writing the least significant byte of the SCSI Output Data Latch (SODL) register will cause the FIFO to load. These functions are summarized in the table below.
Register Name SODL SODL0 SODL1 Register Operation Write Write Write FIFO Function Load Load None
FIFO Bits [15:0] [7:0] [15:8]
Register: 0x50-0x51 (0xD0-0xD1)
SCSI Input Data Latch (SIDL) Read Only
15 SIDL x x x x x x x x x x x x x x x x 0
SIDL
SCSI Input Data Latch [15:0] This register is used primarily for diagnostic testing, programmed I/O operation, or error recovery. Data received from the SCSI bus can be read from this register. Data can be written to the SCSI Output Data Latch (SODL) register and then read back into the LSI53C875 by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs from the SCSI Bus Data Lines (SBDL) register; SCSI Input Data Latch (SIDL) contains latched data and the SCSI Bus Data Lines (SBDL) always contains exactly what is currently on the SCSI data bus. The power-up value of this register is indeterminate.
5-77
Registers: 0x54-0x55 (0xD4-0xD5)
SCSI Output Data Latch (SODL) Read/Write
15 SODL x x x x x x x x x x x x x x x x 0
SODL
SCSI Output Data Latch [15:0] This register is used primarily for diagnostic testing or programmed I/O operation. Data written to this register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCSI Control One (SCNTL1) register. This register is used to send data using programmed I/O. Data flows through this register when sending data in any mode. It is also used to write to the synchronous data FIFO when testing the chip. The power-up value of this register is indeterminate.
Registers: 0x58-0x59 (0xD8-0xD9)
SCSI Bus Data Lines (SBDL) Read Only
15 SBDL x x x x x x x x x x x x x x x x 0
SBDL
SCSI Bus Data Lines [15:0] This register contains the SCSI data bus status. Even though the SCSI data bus is active low, these bits are active high. The signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. This register is used when receiving data using programmed I/O. This register can also be used for diagnostic testing or in low level mode. If the chip is in wide mode SCSI Control Three (SCNTL3), bit 3, SCSI Test Two (STEST2), bit 2 and SCSI Bus Data Lines (SBDL) is read, both byte lanes are checked for parity regardless of phase. When in a nondata phase, this will cause a parity error interrupt to be generated because upper byte lane parity is invalid.
5-78
SCSI Operating Registers
Registers: 0x5C-0x5F (0xDC-0xDF)
Scratch Register B (SCRATCHB) Read/Write
31 SCRATCHB x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
SCRATCHB
Scratch Register B [31:0] This is a general purpose user definable scratch pad register. Apart from CPU access, only register Read/Write and Memory Moves directed at the SCRATCH register will alter its contents. The LSI53C875 cannot fetch SCRIPTS instructions from this location. When bit 3 in the Chip Test Two (CTEST2) register is set, this register contains the base address for the 4 Kbytes internal RAM. Setting Chip Test Two (CTEST2), bit 3 only causes the base address to appear in the Scratch Register B (SCRATCHB) register; any information that was previously in the register remains intact. Any writes to this register while the bit is set pass through to the actual Scratch Register B (SCRATCHB) register. The power-up values are indeterminate.
Registers: 0x60-0x7F (0xE0-0xFF)
Scratch Registers C-J (SCRATCHC-SCRATCHJ) Read/Write These registers are general purpose scratch registers for user-defined functions. The LSI53C875 cannot fetch SCRIPTS instructions from this location. The power-up value of these registers is indeterminate.
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5-80
SCSI Operating Registers
Chapter 6 Instruction Set of the I/O Processor
After power-up and initialization, the LSI53C875 can be operated in the low level register interface mode or in the high level SCSI SCRIPTS mode. Chapter 6 is divided into the following sections:
* * * * * * *
Section 6.1, "SCSI SCRIPTS" Section 6.2, "Block Move Instructions" Section 6.3, "I/O Instruction" Section 6.4, "Read/Write Instructions" Section 6.5, "Transfer Control Instructions" Section 6.6, "Memory Move Instructions" Section 6.7, "Load and Store Instructions"
With the low level register interface mode, the user has access to the DMA control logic and the SCSI bus control logic. An external processor has access to the SCSI bus signals and the low level DMA signals, which allows creation of complicated board level test algorithms. The low level interface is useful for backward compatibility with SCSI devices that require certain unique timings or bus sequences to operate properly. Another feature allowed at the low level is loopback testing. In loopback mode, the SCSI core can be directed to talk to the DMA core to test internal data paths all the way out to the chip's pins.
6.1 SCSI SCRIPTS
To operate in the SCSI SCRIPTS mode, the LSI53C875 requires only a SCRIPTS start address. The start address must be at a longword (four byte) boundary. This aligns subsequent SCRIPTS at a longword
LSI53C875/875E PCI to Ultra SCSI I/O Processor
6-1
boundary since all SCRIPTS are 8 or 12 bytes long. Instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. Once an interrupt is generated, the LSI53C875 halts all operations until the interrupt is serviced. Then, the start address of the next SCRIPTS instruction may be written to the DMA SCRIPTS Pointer (DSP) register to restart the automatic fetching and execution of instructions. The SCSI SCRIPTS mode of execution allows the LSI53C875 to make decisions based on the status of the SCSI bus, which offloads the microprocessor from servicing the numerous interrupts inherent in I/O operations. Given the rich set of SCSI oriented features included in the instruction set, and the ability to re-enter the SCSI algorithm at any point, this high level interface is all that is required for both normal and exception conditions. Switching to low level mode for error recovery should never be required. The following types of SCRIPTS instructions are implemented in the LSI53C875 as shown in Table 6.1: Table 6.1
Instruction Block Move I/O or Read/Write
SCRIPTS Instructions
Description Block Move instruction moves data between the SCSI bus and memory. I/O or Read/Write instructions cause the LSI53C875 to trigger common SCSI hardware sequences, or to move registers. Transfer Control instruction allows SCRIPTS instructions to make decisions based on real time SCSI bus conditions. Memory Move instruction causes the LSI53C875 to execute block moves between different parts of main memory. Load and Store instructions provide a more efficient way to move data to/from memory from/to an internal register in the chip without using the Memory Move instruction.
Transfer Control
Memory Move
Load and Store
6-2
Instruction Set of the I/O Processor
Each instruction consists of two or three 32-bit words. The first 32-bit word is always loaded into the DMA Command (DCMD) and DMA Byte Counter (DBC) registers, the second into the DMA SCRIPTS Pointer Save (DSPS) register. The third word, used only by Memory Move instructions, is loaded into the Temporary (TEMP) shadow register. In an indirect I/O or Move instruction, the first two 32-bit opcode fetches is followed by one or two more 32-bit fetch cycles.
6.1.1 Sample Operation
This operation describes execution of a SCRIPTS instruction for a Block Move instruction.
*
The host CPU, through programmed I/O, gives the DMA SCRIPTS Pointer (DSP) register (in the Operating register file) the starting address in main memory that points to a SCSI SCRIPTS program for execution. Loading the DMA SCRIPTS Pointer (DSP) register causes the LSI53C875 to fetch its first instruction at the address just loaded. This will be from main memory or the internal RAM, depending on the address. The LSI53C875 typically fetches two longwords (64 bits) and decodes the high order byte of the first longword as a SCRIPTS instruction. If the instruction is a Block Move, the lower three bytes of the first longword are stored and interpreted as the number of bytes to be moved. The second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. For a SCSI send operation, the LSI53C875 waits until there is enough space in the DMA FIFO to transfer a programmable size block of data. For a SCSI receive operation, it waits until enough data is collected in the DMA FIFO for transfer to memory. At this point, the LSI53C875 requests use of the PCI bus again to transfer the data. When the LSI53C875 is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the PCI bus. The LSI53C875 stays off the PCI bus until the FIFO can again hold (for a write) or has collected (for a read) enough data to repeat the process.
*
*
*
*
SCSI SCRIPTS
6-3
The process repeats until the internally stored byte count has reached zero. The LSI53C875 releases the PCI bus and then performs another SCRIPTS instruction fetch cycle, using the incremented stored address maintained in the DMA SCRIPTS Pointer (DSP) register. Execution of SCRIPTS instructions continues until an error condition occurs or an interrupt SCRIPTS instruction is received. At this point, the LSI53C875 interrupts the host CPU and waits for further servicing by the host system. It can execute independent Block Move instructions specifying new byte counts and starting locations in main memory. In this manner, the LSI53C875 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or requiring an external DMA controller to be programmed. An overview of this process is presented in Figure 6.1. Figure 6.1 SCRIPTS Overview
System Processor
Write DSA
System Memory
SCSI Initiator Write Example
x x x x x x x x x x Select ATN 0, alt_addr Move from identify_msg_buf, when MSG_OUT Move from cmd_buf, when CMD Move from data_buf when DATA_OUT Move from stat_in_buf, when STATUS Move from msg_in_buf, when MSG_IN Move SCNTL2 & 7F to SCNTL2 Clear ACK Wail disconnect alt2 Int 10
S Y S T E M
Write DSP
U SCRIPTS S
B
Fetch
LSI53C875
SCSI Bus
Table
byte count address byte count address byte count address byte count address Data
Message Buffer Command Buffer Data Buffer Status Buffer
6-4
Instruction Set of the I/O Processor
6.2 Block Move Instructions
Performing a Block Move instruction, bit 5, Source I/O - Memory Enable (SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the DMA Mode (DMODE) register determines whether the source/destination address resides in memory or I/O space. When data is being moved onto the SCSI bus, SIOM controls whether that data comes from I/O or memory space. When data is being moved off of the SCSI bus, DIOM controls whether that data goes to I/O or memory space.
6.2.1 First Dword
IT[1:0] IA Instruction Type-Block Move [31:30]
Indirect Addressing 29 When this bit is cleared, user data is moved to or from the 32-bit data start address for the Block Move instruction. The value is loaded into the chip's address register and incremented as data is transferred. The address of the data to be moved is in the second Dword of this instruction. When set, the 32-bit user data start address for the Block Move is the address of a pointer to the actual data buffer address. The value at the 32-bit start address is loaded into the chip's DMA Next Address (DNAD) register using a third longword fetch (4-byte transfer across the host computer bus). Direct The byte count and absolute address are as follows.
Command Byte Count Address of Data
Indirect Use the fetched byte count, but fetch the data address from the address in the instruction.
Command Byte Count Address of Pointer to Data
Block Move Instructions
6-5
Once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. This indirect feature allows a table of data buffer addresses to be specified. Using the LSI Logic SCSI SCRIPTS assembler, the table offset is placed in the script at compile time. Then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. The logical I/O driver builds a structure of addresses for an I/O rather than treating each address individually. This feature makes it possible to locate SCSI SCRIPTS in a PROM. Note: Do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. Table Indirect 28 When this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the Data Structure Address (DSA) register. Both the transfer count and the source/destination address are fetched from this location. Use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the Data Structure Address (DSA) register, to fetch first the byte count and then the data address. The signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. Sign extended values of all ones for negative values are allowed, but bits [31:24] are ignored.
Command Don't Care Not Used Table Offset
Note:
Do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. Figure 6.2 illustrates the Block Move Instruction register.
6-6
Instruction Set of the I/O Processor
Figure 6.2
Block Move Instruction Register
DCMD Register
DBC Register 543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
I/O C/D MSG/ Opcode Table Indirect Addressing Indirect Addressing (LSI53C700 Family Compatible) 0 - Instruction Type - Block Move 0 - Instruction Type - Block Move 24-Bit Block Move Byte Counter
DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
Prior to the start of an I/O, the Data Structure Address (DSA) register should be loaded with the base address of the I/O data structure. The address may be any address on a longword boundary. After a Table Indirect opcode is fetched, the DSA is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. A subsequent fetch from that address brings the data values into the chip. For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C875. Execution of the move begins at this point.
Block Move Instructions
6-7
SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation. The I/O data structure can begin on any longword boundary and may cross system segment boundaries. There are two restrictions on the placement of pointer data in system memory:
* The eight bytes of data in the MOVE instruction must
be contiguous, as shown below, and
* Indirect data fetches are not available during
execution of a Memory-to-Memory DMA operation.
00 Byte Count Physical Data Address
Opcode 27 This 1-bit field defines the instruction to be executed as a block move (MOVE). Target Mode
OPC 0 1 Instruction Defined MOVE CHMOV
These instructions perform the following steps: 1. The LSI53C875 verifies that it is connected to the SCSI bus as a Target before executing this instruction. 2. The LSI53C875 asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as defined by the Phase Field bits in the instruction. 3. If the instruction is for the command phase, the LSI53C875 receives the first command byte and decodes its SCSI Group Code. - If the SCSI Group Code is either Group 0, Group 1, Group 2, or Group 5, and if the Vendor Unique Enhancement 1 (VUE1) bit (SCSI Control Two (SCNTL2), bit 1) is clear, then the LSI53C875
6-8
Instruction Set of the I/O Processor
overwrites the DMA Byte Counter (DBC) register with the length of the Command Descriptor Block: 6, 10, or 12 bytes. - If the Vendor Unique Enhancement 1 (VUE1) bit (SCSI Control Two (SCNTL2), bit 1) is set, the LSI53C875 receives the number of bytes in the byte count regardless of the group code. - If the Vendor Unique Enhancement 1 bit is clear and group code is vendor unique, the LSI53C875 receives the number of bytes in the count. - If any other Group Code is received, the DMA Byte Counter (DBC) register is not modified and the LSI53C875 requests the number of bytes specified in the DMA Byte Counter (DBC) register. If the DMA Byte Counter (DBC) register contains 0x000000, an illegal instruction interrupt is generated. 4. The LSI53C875 transfers the number of bytes specified in the DMA Byte Counter (DBC) register starting at the address specified in the DMA Next Address (DNAD) register. If the Opcode bit is set and a data transfer ends on an odd byte boundary, the LSI53C875 stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation. This byte is combined with the first byte from the subsequent transfer so that a wide transfer can be completed. 5. If the SATN/ signal is asserted by the Initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. The Disable Halt on Parity Error or ATN bit in the SCSI Control One (SCNTL1) register controls whether the LSI53C875 halts on these conditions immediately, or waits until completion of the current Move.
Block Move Instructions
6-9
Initiator Mode
OPC 0 1 Instruction Defined CHMOV MOVE
These instructions perform the following steps: 1. The LSI53C875 verifies that it is connected to the SCSI bus as an Initiator before executing this instruction. 2. The LSI53C875 waits for an unserviced phase to occur. An unserviced phase is any phase (with SREQ/ asserted) for which the LSI53C875 has not yet transferred data by responding with a SACK/. 3. The LSI53C875 compares the SCSI phase bits in the DMA Command (DCMD) register with the latched SCSI phase lines stored in the SCSI Status One (SSTAT1) register. These phase lines are latched when SREQ/ is asserted. 4. If the SCSI phase bits match the value stored in the SCSI SCSI Status One (SSTAT1) register, the LSI53C875 transfers the number of bytes specified in the DMA Byte Counter (DBC) register starting at the address pointed to by the DMA Next Address (DNAD) register. If the opcode bit is cleared and a data transfer ends on an odd byte boundary, the LSI53C875 stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation, or in the SCSI Output Control Latch (SOCL) register during a send operation. This byte is combined with the first byte from the subsequent transfer so that a wide transfer can complete.
6-10
Instruction Set of the I/O Processor
5. If the SCSI phase bits do not match the value stored in the SCSI Status One (SSTAT1) register, the LSI53C875 generates a phase mismatch interrupt and the instruction is not executed. 6. During a Message-Out phase, after the LSI53C875 has performed a select with Attention (or SATN/ is manually asserted with a Set ATN instruction), the LSI53C875 deasserts SATN/ during the final SREQ/SACK/ handshake. 7. When the LSI53C875 is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction. SCSIP[2:0] SCSI Phase [26:24] This 3-bit field defines the desired SCSI information transfer phase. When the LSI53C875 operates in Initiator mode, these bits are compared with the latched SCSI phase bits in the SCSI Status One (SSTAT1) register. When the LSI53C875 operates in Target mode, the LSI53C875 asserts the phase defined in this field. The following table describes the possible combinations and the corresponding SCSI phase.
MSG C_D 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 I_O 0 1 0 1 0 1 0 1 SCSI Phase Data-Out Data-In Command Status Reserved-Out Reserved-In Message-Out Message-In
TC[23:0]
Transfer Counter [23:0] This 24-bit field specifies the number of data bytes to be moved between the LSI53C875 and system memory. The field is stored in the DMA Byte Counter (DBC) register. When the LSI53C875 transfers data to/from memory, the DBC register is decremented by the number of
Block Move Instructions
6-11
bytes transferred. In addition, the DMA Next Address (DNAD) register is incremented by the number of bytes transferred. This process is repeated until the DBC register has been decremented to zero. At that time, the LSI53C875 fetches the next instruction. If bit 28 is set, indicating table indirect addressing, this field is not used. The byte count is instead fetched from a table pointed to by the Data Structure Address (DSA) register.
6.2.2 Second Dword
Start Address [31:0] This 32-bit field specifies the starting address of the data to move to/from memory. This field is copied to the DMA Next Address (DNAD) register. When the LSI53C875 transfers data to or from memory, the DNAD register is incremented by the number of bytes transferred. When bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. When bit 28 is set, indicating table indirect addressing, the value in this field is an offset into a table pointed to by the Data Structure Address (DSA). The table entry contains byte count and address information.
6.3 I/O Instruction
6.3.1 First Dword
IT[1:0] OPC[2:0] Instruction Type - I/O Instruction [31:30]
Opcode [29:27] The following Opcode bit configurations have different meanings, depending on whether the LSI53C875 is operating in initiator or target mode. Opcode selections 101-111 are considered Read/Write instructions and are described in Section 6.4, "Read/Write Instructions."
Note:
6-12
Instruction Set of the I/O Processor
Target Mode
OPC2 OPC1 OPC0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Instruction Defined Reselect Disconnect Wait Select Set Clear
Reselect Instruction The LSI53C875 arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID (SCID) register. If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. If the LSI53C875 wins arbitration, it attempts to reselect the SCSI device whose ID is defined in the destination ID field of the instruction. Once the LSI53C875 wins arbitration, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register. This way the SCRIPTS can move on to the next instruction before the reselection completes. It continues executing SCRIPTS until a SCRIPT that requires a response from the Initiator is encountered. If the LSI53C875 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C875 to Initiator mode if it is reselected, or to Target mode if it is selected. Disconnect Instruction The LSI53C875 disconnects from the SCSI bus by deasserting all SCSI signal outputs. Wait Select Instruction If the LSI53C875 is selected, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register.
I/O Instruction
6-13
If reselected, the LSI53C875 fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C875 to Initiator mode when it is reselected. If the CPU sets the SIGP bit in the Interrupt Status (ISTAT) register, the LSI53C875 aborts the Wait Select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Set Instruction When the SACK/ or SATN/ bits are set, the corresponding bits in the SCSI Output Control Latch (SOCL) register are set. Do not set SACK/ or SATN/ except for testing purposes. When the target bit is set, the corresponding bit in the SCSI Control Zero (SCNTL0) register is also set. When the carry bit is set, the corresponding bit in the Arithmetic Logic Unit (ALU) is set. Note: None of the signals are set on the SCSI bus in the Target mode. Clear Instruction When the SACK/ or SATN/ bits are cleared, the corresponding bits are cleared in the SCSI Output Control Latch (SOCL) register. Do not set SACK/ or SATN/ except for testing purposes. When the target bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the carry bit is cleared, the corresponding bit in the ALU is cleared. Note: None of the signals are cleared on the SCSI bus in the Target mode. Figure 6.3 illustrates the I/O Instruction register.
6-14
Instruction Set of the I/O Processor
Figure 6.3
I/O Instruction Register
DCMD Register
DBC Register 543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
R
R
R
R
Set/Clear ATN/
Set/Clear ACK/ Set/Clear Target Mode Set/Clear Carry Encoded Destination ID 0 Encoded Destination ID 1 Encoded Destination ID 2 Encoded Destination ID 3 Reserved Reserved Reserved Reserved Select with ATN/ Table Indirect Mode Relative Address Mode Opcode Bit 0 Opcode Bit 1 Opcode Bit 2 1 - Instruction Type - I/O 0 - Instruction Type - I/O Second 32-Bit Word of the I/O Instruction
DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
32-Bit Jump Address
I/O Instruction
6-15
Initiator Mode
OPC2 0 0 0 0 1 OPC1 0 0 1 1 0 OPC0 0 1 0 1 0 Instruction Defined Select Wait Disconnect Wait Reselect Set Clear
Select Instruction The LSI53C875 arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID (SCID) register. If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. If the LSI53C875 wins arbitration, it attempts to select the SCSI device whose ID is defined in the destination ID field of the instruction. Once the LSI53C875 wins arbitration, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register. This way the SCRIPTS can move to the next instruction before the selection completes. It continues executing SCRIPTS until a SCRIPT that requires a response from the Target is encountered. If the LSI53C875 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C875 to Initiator mode if it is reselected, or to Target mode if it is selected. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase. Wait Disconnect Instruction The LSI53C875 waits for the Target to perform a "legal" disconnect from the SCSI bus. A "legal" disconnect occurs when SBSY/ and SSEL/ are inactive for a minimum of one Bus Free delay (400 ns), after the LSI53C875 receives a Disconnect Message or a Command Complete Message.
6-16
Instruction Set of the I/O Processor
Wait Reselect Instruction If the LSI53C875 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C825A to Target mode when it is selected. If the LSI53C875 is reselected, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register. If the CPU sets the SIGP bit in the Interrupt Status (ISTAT) register, the LSI53C875 aborts the Wait Reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Set Instruction When the SACK/ or SATN/ bits are set, the corresponding bits in the SCSI Output Control Latch (SOCL) register are set. When the target bit is set, the corresponding bit in the SCSI Control Zero (SCNTL0) register is also set. When the carry bit is set, the corresponding bit in the ALU is set. Clear Instruction When the SACK/ or SATN/ bits are cleared, the corresponding bits are cleared in the SCSI Output Control Latch (SOCL) register. When the target bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the carry bit is cleared, the corresponding bit in the ALU is cleared. Relative Addressing Mode 26 When this bit is set, the 24-bit signed value in the DMA Next Address (DNAD) register is used as a relative displacement from the current DMA SCRIPTS Pointer (DSP) address. Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions. The Select and Reselect instructions can contain an absolute alternate jump address or a relative transfer address. Table Indirect Mode 25 When this bit is set, the 24-bit signed value in the DMA Byte Counter (DBC) register is added to the value in the
I/O Instruction
6-17
Data Structure Address (DSA) register, and used as an offset relative to the value in the Data Structure Address (DSA) register. The SCSI Control Three (SCNTL3) value, SCSI ID, synchronous offset and synchronous period are loaded from this address. Prior to the start of an I/O, load the Data Structure Address (DSA) with the base address of the I/O data structure. Any address on a longword boundary is allowed. After a Table Indirect opcode is fetched, the Data Structure Address (DSA) is added to the 24-bit signed offset value from the opcode to generate the address of the required data. Both positive and negative offsets are allowed. A subsequent fetch from that address brings the data values into the chip. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation. The I/O data structure can begin on any longword boundary and may cross system segment boundaries. There are two restrictions on the placement of data in system memory:
* The I/O data structure must lie within the 8 Mbytes
above or below the base address.
* An I/O command structure must have all four bytes
contiguous in system memory, as shown below. The offset/period bits are ordered as in the SCSI Transfer (SXFER) register. The configuration bits are ordered as in the SCSI Control Three (SCNTL3) register.
Config ID Offset/period 00
Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions. Use bits 25 and 26 individually or in combination to produce the following conditions:
Bit 25 0 0 1 1 Bit 26 0 1 0 1 Addressing Mode Direct Table Indirect Relative Table Relative
6-18
Instruction Set of the I/O Processor
Direct Uses the device ID and physical address in the instruction.
Command ID Not Used Not Used
Absolute Alternate Address
Table Indirect Uses the physical jump address, but fetches data using the table indirect method.
Command Table Offset Absolute Alternate Address
Relative Uses the device ID in the instruction, but treats the alternate address as a relative jump.
Command ID Not Used Not Used
Absolute Jump Offset
Table Relative Treats the alternate jump address as a relative jump and fetches the device ID, synchronous offset, and synchronous period indirectly. The value in bits [23:0] of the first four bytes of the SCRIPTS is added to the data structure base address to form the fetch address.
Command Table Offset Alternate Jump Offset
Sel
Select with ATN/ 24 This bit specifies whether SATN/ is asserted during the selection phase when the LSI53C875 is executing a Select instruction. When operating in Initiator mode, set this bit for the Select instruction. If this bit is set on any other I/O instruction, an illegal instruction interrupt is generated.
I/O Instruction
6-19
R ENDID[3:0]
Reserved
[23:20]
Encoded SCSI Destination ID [19:16] This 4-bit field specifies the destination SCSI ID for an I/O instruction. Reserved [15:11]
R CC
Set/Clear Carry 10 This bit is used in conjunction with a Set or Clear instruction to set or clear the Carry bit. Setting this bit with a Set instruction asserts the Carry bit in the ALU. Clearing this bit with a Clear instruction deasserts the Carry bit in the ALU. Set/Clear Target Mode 9 This bit is used in conjunction with a Set or Clear instruction to set or clear Target mode. Setting this bit with a Set instruction configures the LSI53C875 as a Target device (this sets bit 0 of the SCSI Control Zero (SCNTL0) register). Clearing this bit with a Clear instruction configures the LSI53C875 as an Initiator device (this clears bit 0 of the SCNTL0 register). Reserved Set/Clear SACK/ Reserved [8:7] 6 [5:4]
TM
R ACK R ATN
Set/Clear SATN/ 3 These two bits are used in conjunction with a Set or Clear instruction to assert or deassert the corresponding SCSI control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3 controls the SCSI SATN/ signal. Setting either of these bits will set or reset the corresponding bit in the SCSI Output Control Latch (SOCL) register, depending on the instruction used. The Set instruction is used to assert SACK/ and/or SATN/ on the SCSI bus. The Clear instruction is used to deassert SACK/ and/or SATN/ on the SCSI bus. Since SACK/ and SATN/ are Initiator signals, they are not asserted on the SCSI bus unless the LSI53C875 is operating as an Initiator or the SCSI Loopback Enable bit is set in the SCSI Status Two (SSTAT2) register.
6-20
Instruction Set of the I/O Processor
The Set/Clear SCSI ACK/ATN instruction is used after message phase Block Move operations to give the Initiator the opportunity to assert attention before acknowledging the last message byte. For example, if the initiator wishes to reject a message, is issues an Assert SCSI ATN instruction before a Clear SCSI ACK instruction. R Reserved [2:0]
6.3.2 Second Dword
SA Start Address [31:0] This 32-bit field contains the memory address to fetch the next instruction if the selection or reselection fails. If relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current DMA SCRIPTS Pointer (DSP) register value.
6.4 Read/Write Instructions
The Read/Write instruction supports addition, subtraction, and comparison of two separate values within the chip. It performs the desired operation on the specified register and the SCSI First Byte Received (SFBR) register, then stores the result back to the specified register or the SFBR.
6.4.1 First Dword
IT[1:0] Instruction Type - Read/Write Instruction [31:30] The Read/Write instruction uses operator bits 26 through 24 in conjunction with the opcode bits to determine which instruction is currently selected. Opcode [29:27] The combinations of these bits determine if the instruction is a Read/Write or an I/O instruction. Opcodes 000 through 100 are considered I/O instructions.
OPC[2:0]
Read/Write Instructions
6-21
O[2:0]
Operator [26:24] These bits are used in conjunction with the opcode bits to determine which instruction is currently selected. Refer to Table 6.1 for field definitions. Use data8/SFBR 23 When this bit is set, SFBR is used instead of the data8 value during a Read-Modify-Write instruction (see Table 6.1). This allows the user to add two register values. Register Address - A[6:0] [22:16] It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SFBR cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C875. Immediate Data [15:8] This 8-bit value is used as a second operand in logical and arithmetic functions. Reserved [7:0]
D8
A[6:0]
ImmD
R
6.4.2 Second Dword
Destination Address [31:0] This field contains the 32-bit destination address where the data to move.
6.4.3 Read-Modify-Write Cycles
During these cycles the register is read, the selected operation is performed, and the result is written back to the source register. The Add operation is used to increment or decrement register values (or memory values if used in conjunction with a Memory-to-Register Move operation) for use as loop counters. Subtraction is not available when SFBR is used instead of data8 in the instruction syntax. To subtract one value from another when using SFBR, first XOR the value to subtract (subtrahend) with 0xFF, and add 1 to the resulting value. This creates the 2's complement of the subtrahend. The two values are then added to obtain the difference.
6-22
Instruction Set of the I/O Processor
Figure 6.4 illustrates the Read/Write Instruction register.
Figure 6.4
Read/Write Instruction Register
DCMD Register
DBC Register 543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Immediate Data A0 A1 A2 A3 A4 A5 A6 use data8/SFBR Operator 0 Operator 1 Operator 2 Opcode Bit 0 Opcode Bit 1 Opcode Bit 2 1 - Instruction Type - R/W 0 - Instruction Type - R/W Register Address
Reserved (must be 0)
DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
Read/Write Instructions
6-23
6.4.4 Move To/From SFBR Cycles
All operations are read-modify-writes. However, two registers are involved, one of which is always the SFBR. Table 6.2 shows the possible read-modify-write operations. The possible functions of this instruction are:
* * * * *
Table 6.2
Write one byte (value contained within the SCRIPTS instruction) into any chip register. Move to/from the SFBR from/to any other register. Alter the value of a register with AND, OR, ADD, XOR, SHIFT LEFT, or SHIFT RIGHT operators. After moving values to the SFBR, the compare and jump, call, or similar instructions are used to check the value. A Move-to-SFBR followed by a Move-from-SFBR is used to perform a register-to-register move.
Read/Write Instructions
Opcode 111 Read-Modify-Write Move data into register. Syntax: "Move data8 to RegA" Shift register one bit to the left and place the result in the same register. Syntax: "Move RegA SHL RegA" Opcode 110 Move to SFBR Move data into SCSI First Byte Received (SFBR) register. Syntax: "Move data8 to SFBR" Shift register one bit to the left and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA SHL SFBR" OR data with register and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA | data8 to SFBR" XOR data with register and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA XOR data8 to SFBR" Opcode 101 Move from SFBR Move data into register. Syntax: "Move data8 to RegA" Shift the SCSI First Byte Received (SFBR) register one bit to the left and place the result in the register. Syntax: "Move SFBR SHL RegA" OR data with SFBR and place the result in the register. Syntax: "Move SFBR | data8 to RegA" XOR data with SFBR and place the result in the register. Syntax: "Move SFBR XOR data8 to RegA"
Operator 000
0011
010
OR data with register and place the result in the same register. Syntax: "Move RegA | data8 to RegA" XOR data with register and place the result in the same register. Syntax: "Move RegA XOR data8 to RegA"
011
6-24
Instruction Set of the I/O Processor
Table 6.2
Read/Write Instructions (Cont.)
Opcode 111 Read-Modify-Write AND data with register and place the result in the same register. Syntax: "Move RegA & data8 to RegA" Shift register one bit to the right and place the result in the same register. Syntax: "Move RegA SHR RegA" Opcode 110 Move to SFBR AND data with register and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA & data8 to SFBR" Shift register one bit to the right and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA SHR SFBR" Add data to register without carry and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA + data8 to SFBR" Add data to register with carry and place the result in the SCSI First Byte Received (SFBR) register. Syntax: "Move RegA + data8 to SFBR with carry" Opcode 101 Move from SFBR AND data with SFBR and place the result in the register. Syntax: "Move SFBR & data8 to RegA" Shift the SCSI First Byte Received (SFBR) register one bit to the right and place the result in the register. Syntax: "Move SFBR SHR RegA" Add data to SFBR without carry and place the result in the register. Syntax: "Move SFBR + data8 to RegA"
Operator 100
1011
110
Add data to register without carry and place the result in the same register. Syntax: "Move RegA + data8 to RegA" Add data to register with carry and place the result in the same register. Syntax: "Move RegA + data8 to RegA with carry"
111
Add data to SFBR with carry and place the result in the register. Syntax: "Move SFBR + data8 to RegA with carry"
1. Data is shifted through the Carry bit and the Carry bit is shifted into the data byte. Miscellaneous Notes: Substitute the desired register name or address for "RegA" in the syntax examples. data8 indicates eight bits of data. Use SCSI First Byte Received (SFBR) instead of data8 to add two register values.
Read/Write Instructions
6-25
6.5 Transfer Control Instructions
6.5.1 First Dword
IT[1:0] OPC[2:0] Instruction Type Transfer Control Instruction [31:30]
Opcode [29:27] This 3-bit field specifies the type of Transfer Control Instruction to execute. All Transfer Control Instructions can be conditional. They can be dependent on a true/false comparison of the ALU Carry bit or a comparison of the SCSI information transfer phase with the Phase field, and/or a comparison of the First Byte Received with the Data Compare field. Each instruction can operate in Initiator or Target mode.
OPC2 0 0 0 0 1 OPC1 0 0 1 1 x OPC0 0 1 0 1 x Instruction Defined Jump Call Return Interrupt Reserved
Jump Instruction The LSI53C875 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare and True/False bit fields. If the comparisons are true, it loads the DMA SCRIPTS Pointer (DSP) register with the contents of the DMA SCRIPTS Pointer Save (DSPS) register. The DSP register now contains the address of the next instruction. If the comparisons are false, the LSI53C875 fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register, leaving the instruction pointer unchanged.
6-26
Instruction Set of the I/O Processor
Call Instruction The LSI53C875 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields. If the comparisons are true, it loads the DMA SCRIPTS Pointer (DSP) register with the contents of the DMA SCRIPTS Pointer Save (DSPS) register and that address value becomes the address of the next instruction. When the LSI53C875 executes a Call instruction, the instruction pointer contained in the DMA SCRIPTS Pointer (DSP) register is stored in the TEMP register. Since the Temporary (TEMP) register is not a stack and can only hold one longword, nested call instructions are not allowed. If the comparisons are false, the LSI53C875 fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register and the instruction pointer is not modified. Figure 6.5 illustrates the Transfer Control instruction.
Transfer Control Instructions
6-27
Figure 6.5
Transfer Control Instructions
DCMD Register
DBC Register 543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Mask for Compare Wait for Valid Phase Compare Phase Compare Data Jump if: True=1, False=0 Interrupt on the Fly Carry Test 0 (Reserved) Relative Addressing Mode I/O C/D MSG Opcode Bit 0 Opcode Bit 1 Opcode Bit 2 1 - Instruction Type - Transfer Control 0 - Instruction Type - Transfer Control
Data to be compared with the SCSI First Byte Received
DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
6-28
Instruction Set of the I/O Processor
Return Instruction The LSI53C875 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields. If the comparisons are true, then it loads the DMA SCRIPTS Pointer (DSP) register with the contents of the DMA SCRIPTS Pointer Save (DSPS) register. That address value becomes the address of the next instruction. When a Return instruction is executed, the value stored in the Temporary (TEMP) register is returned to the DMA SCRIPTS Pointer (DSP) register. The LSI53C875 does not check to see whether the Call instruction has already been executed. It does not generate an interrupt if a Return instruction is executed without previously executing a Call instruction. If the comparisons are false, then the LSI53C875 fetches the next instruction from the address pointed to by the DSP register and the instruction pointer is not modified. Interrupt Instruction The LSI53C875 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields. If the comparisons are true, then the LSI53C875 generates an interrupt by asserting the IRQ/ signal. The 32-bit address field stored in the DMA SCRIPTS Pointer Save (DSPS) register can contain a unique interrupt service vector. When servicing the interrupt, this unique status code allows the Interrupt Service Routine to quickly identify the point at which the interrupt occurred. The LSI53C875 halts and the DMA SCRIPTS Pointer (DSP) register must be written to start any further operation. Interrupt-on-the-Fly Instruction The LSI53C875 can do a true/false comparison of the ALU carry bit or compare the phase and/or data as defined by the Phase Compare, Data Compare, and
Transfer Control Instructions
6-29
True/False bit fields. If the comparisons are true, and the Interrupt-on-the-Fly bit is set (bit 2), the LSI53C875 asserts the Interrupt-on-the-Fly bit. SCSIP[2:0] SCSI Phase [26:24] This 3-bit field corresponds to the three SCSI bus phase signals that are compared with the phase lines latched when SREQ/ is asserted. Comparisons can be performed to determine the SCSI phase actually being driven on the SCSI bus. The following table describes the possible combinations and their corresponding SCSI phase. These bits are only valid when the LSI53C875 is operating in Initiator mode. Clear these bits when the LSI53C875 is operating in the Target mode.
MSG 0 0 0 0 1 1 1 1 C/D 0 0 1 1 0 0 1 1 I/O 0 1 0 1 0 1 0 1 SCSI Phase Data-Out Data-In Command Status Reserved-Out Reserved-In Message-Out Message-In
RA
Relative Addressing Mode 23 When this bit is set, the 24-bit signed value in the DMA SCRIPTS Pointer Save (DSPS) register is used as a relative offset from the current DMA SCRIPTS Pointer (DSP) address (which is pointing to the next instruction, not the one currently executing). The relative mode does not apply to Return and Interrupt SCRIPTS. Jump/Call an Absolute Address Start execution at the new absolute address.
Command Condition Codes Absolute Alternate Address
Jump/Call a Relative Address Start execution at the current address plus (or minus) the relative offset.
6-30
Instruction Set of the I/O Processor
Command Don't Care
Condition Codes Alternate Jump Offset
The SCRIPTS program counter is a 32-bit value pointing to the SCRIPT currently being executed by the LSI53C875. The next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the Jump or Call instruction. Because it is signed (2's complement), the jump can be forward or backward. A relative transfer can be to any address within a 16 Mbyte segment. The program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. SCRIPTS programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing SCRIPTS. For example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. If a SCRIPT is written using only relative transfers it does not require any run time alteration of physical addresses, and could be stored in and executed from a PROM. CT Carry Test 21 When this bit is set, decisions based on the ALU carry bit can be made. True/False comparisons are legal, but Data Compare and Phase Compare are illegal. Interrupt-on-the-Fly 20 When this bit is set, the interrupt instruction does not halt the SCRIPTS processor. Once the interrupt occurs, the Interrupt-on-the-Fly bit (Interrupt Status (ISTAT), bit 2) is asserted. Jump If True/False 19 This bit determines whether the LSI53C875 branches when a comparison is true or when a comparison is false. This bit applies to phase compares, data compares, and carry tests. If both the Phase Compare and Data Compare bits are set, then both compares must be true to branch on a true condition. Both compares must be false to branch on a false condition.
IF
JMP
Transfer Control Instructions
6-31
Bit 19 0 0 1 1
Result of Compare False True False True
Action Jump Taken No Jump No Jump Jump Taken
CD
Compare Data 18 When this bit is set, the first byte received from the SCSI data bus (contained in SCSI First Byte Received (SFBR) register) is compared with the Data to be Compared Field in the Transfer Control instruction. The Wait for Valid Phase bit controls when this compare occurs. The Jump if True/False bit determines the condition (true or false) to branch on. Compare Phase 17 When the LSI53C875 is in Initiator mode, this bit controls phase compare operations. When this bit is set, the SCSI phase signals (latched by SREQ/) are compared to the Phase Field in the Transfer Control instruction. If they match, the comparison is true. The Wait for Valid Phase bit controls when the compare occurs. When the LSI53C875 is operating in Target mode and this bit is set, it tests for an active SCSI SATN/ signal. Wait For Valid Phase 16 If the Wait for Valid Phase bit is set, the LSI53C875 waits for a previously unserviced phase before comparing the SCSI phase and data. If the Wait for Valid Phase bit is cleared, the LSI53C875 compares the SCSI phase and data immediately.
CP
WVP
DCM
Data Compare Mask [15:8] The Data Compare Mask allows a SCRIPT to test certain bits within a data byte. During the data compare, if any mask bits are set, the corresponding bit in the SCSI First Byte Received (SFBR) data byte is ignored. For instance, a mask of 01111111b and data compare value of 1XXXXXXXb allows the SCRIPTS processor to determine whether or not the high order bit is set while ignoring the remaining bits.
6-32
Instruction Set of the I/O Processor
DCV
Data Compare Value [7:0] This 8-bit field is the data to be compared against the register. These bits are used in conjunction with the Data Compare Mask Field to test for a particular data value.
6.5.2 Second Dword
Jump Address [31:0] This 32-bit field contains the address of the next instruction to fetch when a jump is taken. Once the LSI53C875 fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the DMA SCRIPTS Pointer (DSP) register and becomes the current instruction pointer.
6.6 Memory Move Instructions
For Memory Move instructions, bits 5 and 4 (SIOM and DIOM) in the DMA Mode (DMODE) register determine whether the source or destination addresses reside in memory or I/O space. By setting these bits appropriately, data may be moved within memory space, within I/O space, or between the two address spaces. The Memory Move instruction is used to copy the specified number of bytes from the source address to the destination address. Allowing the LSI53C875 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers. Up to 16 Mbytes may be transferred with one instruction. There are two restrictions:
*
Both the source and destination addresses must start with the same address alignment A[1:0]. If the source and destination are not aligned, then an illegal instruction interrupt occurs. For the PCI Cache Line Size register setting to take effect, the source and destination must be the same distance from a cache line boundary. Indirect addresses are not allowed. A burst of data is fetched from the source address, put into the DMA FIFO and then written out to the destination address. The move continues until the byte count decrements to zero, then another SCRIPTS is fetched from system memory.
*
Memory Move Instructions
6-33
The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address (DSA) registers are additional holding registers used during the Memory Move. However, the contents of the Data Structure Address (DSA) register are preserved. IT[2:0] R Instruction Type - Memory Move [31:39]
Reserved [28:25] These bits are reserved and must be zero. If any of these bits are set, an illegal instruction interrupt occurs. No Flush 24 When this bit is set, the LSI53C875 performs a Memory Move without flushing the prefetch unit. When this bit is clear, the Memory Move instruction automatically flushes the prefetch unit. Use the No Flush option if the source and destination are not within four instructions of the current Memory Move instruction. Note: This bit has no effect unless the Prefetch Enable bit in the DMA Control (DCNTL) register is set. For information on SCRIPTS instruction prefetching, see Chapter 2, "Functional Description." Transfer Count [23:0] The number of bytes to be transferred is stored in the lower 24 bits of the first instruction word.
NF
TC[23:0]
6.6.1 Read/Write System Memory from SCRIPTS
By using the Memory Move instruction, single or multiple register values are transferred to or from system memory. Because the LSI53C875 responds to addresses as defined in the Base Address Zero (I/O) or Base Address One (Memory) registers, it can be accessed during a Memory Move operation if the source or destination address decodes to within the chip's register space. If this occurs, the register indicated by the lower seven bits of the address is taken as the data source or destination. In this way, register values are saved to system memory and later restored, and SCRIPTS can make decisions based on data values in system memory.
6-34
Instruction Set of the I/O Processor
The SFBR is not writable using the CPU, and therefore not by a Memory Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, first move the byte to an intermediate LSI53C875 register (for example, a SCRATCH register), and then to the SFBR. The same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers.
6.6.2 Second Dword
DSPS Register [31:0] These bits contain the source address of the Memory Move.
6.6.3 Third Dword
TEMP Register [31:0] These bits contain the destination address for the Memory Move. Figure 6.6 illustrates the Memory Move instruction.
Memory Move Instructions
6-35
Figure 6.6
Memory Move Instruction
DCMD Register
DBC Register 543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
No Flush 0 (Reserved) 0 (Reserved) 0 (Reserved) 0 (Reserved) 0 - Instruction Type - Memory Move 1 - Instruction Type - Memory Move 1 - Instruction Type - Memory Move 24-Bit Memory Move Byte Counter
DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
TEMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
6-36
Instruction Set of the I/O Processor
6.7 Load and Store Instructions
The Load and Store instructions provide a more efficient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. The Load and Store instructions are represented by two Dword opcodes. The first Dword contains the DMA Command (DCMD) and DMA Byte Counter (DBC) register values. The second Dword contains the DMA SCRIPTS Pointer Save (DSPS) value. This is either the actual memory location of where to Load or Store, or the offset from the Data Structure Address (DSA), depending on the value of bit 28 (DSA Relative). A maximum of 4 bytes may be moved with these instructions. The register address and memory address must have the same byte alignment, and the count set such that it does not cross Dword boundaries. The destination memory address in the Store instruction and the source memory address of the Load instruction may not map back to the operating register set of the chip. This excludes the SCRIPTS RAM and ROM memory spaces. If it does, a PCI read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (Illegal Instruction Detected) immediately following.
Bit A1 0 0 1 1
Bit A0 0 1 0 1
Number of Bytes Allowed to Load and Store One, two, three or four One, two, or three One or two One
The SIOM and DIOM bits in the DMA Mode (DMODE) register determine whether the destination or source address of the instruction is in Memory space or I/O space, as illustrated in the following table. The Load and Store utilizes the PCI commands for I/O read and I/O write to access the I/O space.
Load and Store Instructions
6-37
Bit SIOM (Load) DIOM (Store)
Source Memory Register
Destination Register Memory
6.7.1 First Dword
IT[2:0] Instruction Type [31:29] These bits should be 111, indicating the Load and Store instruction. DSA Relative 28 When this bit is cleared, the value in the DMA SCRIPTS Pointer Save (DSPS) is the actual 32-bit memory address used to perform the Load and Store to/from. When this bit is set, the chip determines the memory address to perform the Load and Store to/from by adding the 24-bit signed offset value in the DMA SCRIPTS Pointer Save (DSPS) to the Data Structure Address (DSA). Reserved [27:26]
DSA
R NF
No Flush (Store instruction only) 25 When this bit is set, the LSI53C875 performs a Store without flushing the prefetch unit. When this bit is cleared, the Store instruction automatically flushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction. This bit has no effect on the Load instruction. Note: This bit has no effect unless the Prefetch Enable bit in the DMA Control (DCNTL) register is set. For information on SCRIPTS instruction prefetching, see Chapter 2, "Functional Description." Load/Store 24 When this bit is set, the instruction is a Load. When cleared, it is a Store.
LS
6-38
Instruction Set of the I/O Processor
R RA[6:0]
Reserved
23
Register Address [22:16] A[6:0] selects the register to Load and Store to/from within the LSI53C875. It is not possible to Load the SCSI First Byte Received (SFBR) register, although it is possible to store the SFBR contents to another location. Reserved [15:3]
Note:
R BC
Byte Count [2:0] This value is the number of bytes to Load and Store.
6.7.2 Second Dword
Memory/IO Address/DSA Offset [31:0] This is the actual memory location of where to Load and Store, or the offset from the Data Structure Address (DSA) register value. Figure 6.7 illustrates the Load and Store Instruction format.
Load and Store Instructions
6-39
Figure 6.7
Load and Store Instruction Format
DCMD Register
DBC Register 543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Reserved (must be 0) A0 A1 A2 A3 A4 A5 A6 0 (Reserved) Load/Store No Flush 0 - Reserved 0 - Reserved DSA Relative 1 1 1 Instruction Type - Load and Store Register Address
Byte Count (Number of bytes to load/store)
DSPS Register - Memory/ I/O Address/DSA Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 543210
6-40
Instruction Set of the I/O Processor
Chapter 7 Instruction Set of the I/O Processor
This chapter specifies the LSI53C875 electrical and mechanical characteristics. It is divided into the following sections:
* * * * * * *
Section 7.1, "DC Characteristics" Section 7.2, "TolerANT Technology Electrical Characteristics" Section 7.3, "AC Characteristics" Section 7.4, "PCI and External Memory Interface Timing Diagrams" Section 7.5, "PCI and External Memory Interface Timing" Section 7.6, "SCSI Timing Diagrams" Section 7.7, "Package Drawings"
7.1 DC Characteristics
This section describes the LSI53C875 DC characteristics. Table 7.1 through Table 7.14 give current and voltage specifications. Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied.
LSI53C875/875E PCI to Ultra SCSI I/O Processor
7-1
Table 7.1
Symbol TSTG VDD VIN ILP1 ESD
2
Absolute Maximum Stress Ratings
Parameter Storage temperature Supply voltage Input voltage Latch-up current Electrostatic discharge Min -55 -0.5 VSS -0.5 150 - Max 150 7.0 VDD +0.5 - 2K Unit C V V mA V Test Conditions - - - - MIL-STD 883C, Method 3015.7
1. - 2 V < VPIN < 8 V. 2. SCSI pins only. Note: Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied.
Table 7.2
Symbol VDD IDD TA
Operating Conditions
Parameter Supply voltage Supply current (dynamic) Supply current (static) Operating free air Thermal resistance (junction to ambient air) Min 4.75 - - 0 - Max 5.25 130 1 70 67 Unit V mA mA C C/W Test Conditions - - - - -
JA
Note: Conditions that exceed the operating limits may cause the device to function incorrectly.
7-2
Instruction Set of the I/O Processor
Table 7.3
Symbol VIH VIL VOH1 VOL IOZ
SCSI Signals--SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
Parameter Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage Min 2.0 VSS -0.5 2.5 VSS -10 Max VDD +0.5 0.8 3.5 0.5 10 Unit V V V V A Test Conditions - - 2.5 mA 48 mA -
1. TolerANT active negation enabled.
Table 7.4
Symbol VIH VIL VOL IOZ
SCSI Signals--SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
Parameter Input high voltage Input low voltage Output low voltage 3-state leakage (SRST/ only) Min 2.0 VSS -0.5 VSS -10 -500 Max VDD +0.5 0.8 0.5 10 -50 Unit V V V A Test Conditions - - 48 mA -
Table 7.5
Input Signals--CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/
Parameter Input high voltage Input low voltage Input leakage Min 2.0 VSS -0.5 -10 Max VDD +0.5 0.8 10 Unit V V A Test Conditions - - -
Symbol VIH VIL IIN
Note: SCLK and BIG_LIT/ have 100 A pull-ups, and GNT/ and IDSEL have 25 A pull-ups, that are enabled when TESTIN is low. TESTIN has a 100 A pull-up that is always enabled.
DC Characteristics
7-3
Table 7.6
Symbol CI CIO
Capacitance
Parameter Input capacitance of input pads Input capacitance of I/O pads Min - - Max 7 10 Unit pF pF Test Conditions - -
Table 7.7
Symbol VOH VOL IOZ
Output Signals--MAC/_TESTOUT, REQ/
Parameter Output high voltage Output low voltage 3-state leakage Min 2.4 VSS -10 Max VDD 0.4 10 Unit V V A Test Conditions -16 mA 16 mA -
Note: REQ/ has a 100 A pull-up that is enabled when TESTIN is low.
Table 7.8
Output Signals--IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/, MOE/, MWE/
Parameter Output high voltage Output low voltage 3-state leakage Min 2.4 VSS -10 Max VDD 0.4 10 Unit V V A Test Conditions -4 mA1 4 mA1 -
Symbol VOH VOL IOZ
1. For IRQ/, Test Conditions are 8 mA. Note: IRQ/, MAS/[1:0], MCE/, MOE/, and MWE/ have a 100 A pull-up that is enabled when TESTIN is low. IRQ/ can be enabled with a register as an open drain with an internal 100 A pull-up.
Table 7.9
Output Signal--SERR/
Min VSS -10 Max 0.4 10 Unit V A Test Conditions 16 mA -
Symbol Parameter VOL IOZ Output low voltage 3-state leakage
7-4
Instruction Set of the I/O Processor
Table 7.10
Bidirectional Signals--AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
Min 2.0 VSS -0.5 2.4 VSS -10 Max VDD +0.5 0.8 VDD 0.4 10 Unit V V V V A Test Conditions - - 16 mA 16 mA -
Symbol Parameter VIH VIL vOH vOL IOZ Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage
Note: All the signals in this table have 25 A pull-ups that are enabled when TESTIN is low.
Table 7.11
Bidirectional Signals--GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4
Parameter Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage Min 2.0 VSS -0.5 2.4 VSS -10 Max VDD +0.5 0.8 VDD 0.4 10 Unit V V V V A Test Conditions - - -16 mA 16 mA -
Symbol VIH VIL VOH VOL IOZ
Note: All the signals in this table have 100 A pull-ups that are enabled when TESTIN is low.
DC Characteristics
7-5
Table 7.12
Symbol VIH VIH VIL VIL VOH VOL IOZ
Bidirectional Signals--MAD[7:0]
Parameter Input high voltage Input high voltage - external memory pull-downs Input low voltage Input low voltage - external memory pull-downs Output high voltage Output low voltage 3-state leakage Min 2.0 3.85 VSS -0.5 VSS -0.5 2.4 VSS -10 Max VDD +0.5 VDD +0.5 0.8 1.35 VDD 0.4 10 Unit Test Conditions V V V V V V A - - - - -4 mA 4 mA -
Note: All the signals in this table have 100 A pull-ups that are enabled when TESTIN is low.
Table 7.13
Input Signals--TDI, TMS, TCK (LSI53C875J, LSI53C875JB, LSI53C875N Only)
Parameter Input high voltage Input low voltage Input leakage Min 3.85 VSS -0.5 -800 Max VDD +0.5 1.35 -200 Unit V V A Test Conditions - - -
Symbol VIH VIL IIN
Table 7.14
Symbol VOH VOL IOZ
Output Signal--TDO (LSI53C875, LSI53C875JB, LSI53C875N Only)
Parameter Output high voltage Output low voltage 3-state leakage Min VDD -0.5 VSS -10 Max VDD 0.5 10 Unit V V A Test Conditions -4 mA 4 mA -
7-6
Instruction Set of the I/O Processor
7.2 TolerANT Technology Electrical Characteristics
The LSI53C875 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators. Table 7.15 provides electrical characteristics for SE SCSI signals. Figure 7.1 through Figure 7.5 provide reference information for testing SCSI signals. Table 7.15
Symbol VOH
1
TolerANT Technology Electrical Characteristics
Min 2.5 0.1 2.0 -0.5 -0.66 1.1 1.5 200 2.5 100 - - - - 20 - 9.7 5.2 0.15 0.19 Max 3.5 0.5 7.0 0.8 -0.77 1.3 1.7 400 24 200 625 95 10 -10 - 10 18.5 14.7 0.49 0.67 Unit V V V V V V V mV mA mA mA mA A A M pF ns ns V/ns V/ns Test Conditions IOH = 2.5 mA IOL = 48 mA - Referenced to VSS VDD = 4.75; II = -20 mA - - - VOH = 2.5 V VOL = 0.5 V Output driving low, pin shorted to VDD supply2 Output driving high, pin shorted to VSS supply -0.5 < VDD < 5.25 VPIN = 2.7 V -0.5 < VDD < 5.25 VPIN = 0.5 V SCSI pins3 PQFP Figure 7.1 Figure 7.1 Figure 7.1 Figure 7.1
Parameter Output high voltage Output low voltage Input high voltage Input low voltage Input clamp voltage Threshold, HIGH to LOW Threshold, LOW to HIGH Output high current Output low current Short-circuit output high current Short-circuit output low current Input high leakage Input low leakage Input resistance Capacitance per pin Rise time, 10% to 90% Fall time, 90% to 10% Slew rate, LOW to HIGH Slew rate, HIGH to LOW
VOL VIH VIL VIK VTH VTL IOH
1
VTH-VTL Hysteresis IOL IOSH1 IOSL ILH ILL RI CP tR
1
tF dVH/dt dVL/dt
TolerANT Technology Electrical Characteristics
7-7
Table 7.15
Symbol ESD
TolerANT Technology Electrical Characteristics
Min 2 100 20 40 Max - - 30 60 Unit kV mA ns ns Test Conditions MIL-STD-883C; 3015-7 - Figure 7.2 Figure 7.2
Parameter Electrostatic discharge Latch-up Filter delay Extended filter delay
1. Active negation outputs only: Data, Parity, SREQ/, SACK/. 2. Single pin only; irreversible damage may occur if sustained for one second. 3. SCSI RESET pin has 10 k pull-up resistor. Note: These values are guaranteed by periodic characterization; they are not 100% tested on every device.
Figure 7.1
Rise and Fall Time Test Conditions
47
20 pF
+ -
2.5 V
Figure 7.2
SCSI Input Filtering
t1
REQ/ or ACK/ Input
VTH
Note: t1 is the input filtering period.
7-8
Instruction Set of the I/O Processor
Figure 7.3
Hysteresis of SCSI Receiver
1.1 1.3
1 Receiving Logic Level 0 1.5 1.7
Input Voltage (Volts)
Figure 7.4
+40
Input Current as a Function of Input Voltage
Input Current (milliAmperes)
+20 14.4 V 8.2 V 0 - 0.7 V HIGH-Z -20 OUTPUT ACTIVE
-40 -4 0 4 8 12 16 Input Voltage (Volts)
TolerANT Technology Electrical Characteristics
7-9
Figure 7.5
Output Sink Current (milliamperes) 0
Output Current as Function of Output Voltage
Output Source Current (milliamperes) 100 80 60 40 20 0 0 1 2 3 4 5 Output Voltage (Volts)
-200 -400 -600 -800 0 1 2 3 4 5 Output Voltage (Volts)
7.3 AC Characteristics
The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 7.1, "DC Characteristics"). Chip timings are based on simulation at worst case voltage, temperature, and processing. Timings were developed with a load capacitance of 50 pF. Table 7.16 and Figure 7.6 provide External Clock timing data.
7-10
Instruction Set of the I/O Processor
Table 7.16
Symbol t1
Clock Timing
Parameter Bus clock cycle time SCSI clock cycle time (SCLK)1 Min 30 12.5 12 5 12 5 1 1 Max DC 60 - - - - - - Unit ns ns ns ns ns ns V/ns V/ns
t2
CLK LOW time2 SCLK LOW time2
t3
CLK HIGH time
2
SCLK HIGH time2 t4 CLK slew rate SCLK slew rate
1. This parameter must be met to ensure SCSI timings are within specification. 2. Duty cycle not to exceed 60/40.
Figure 7.6
Clock Waveforms
t3 t1
CLK, SCLK t2 t4
AC Characteristics
7-11
Table 7.17 and Figure 7.7 provide Reset Input timing data. Table 7.17
Symbol t1 t2 t3 t4
Reset Input
Parameter Reset pulse width Reset deasserted setup to CLK HIGH MAD setup time to CLK HIGH (for configuring the MAD bus only) MAD hold time from CLK HIGH (for configuring the MAD bus only) Min 10 0 20 20 Max - - - - Unit tCLK ns ns ns
Figure 7.7
CLK
Reset Input
t1 RST/
t2
t3 MAD1 1. When enabled.
t4
Valid Data
7-12
Instruction Set of the I/O Processor
Table 7.18 and Figure 7.8 provide Interrupt Output timing data. Table 7.18
Symbol t1 t2 t3
Interrupt Output
Parameter CLK HIGH to IRQ/ LOW CLK HIGH to IRQ/ HIGH IRQ/ deassertion time Min 20 40 3 Max - - - Unit ns ns CLK
Figure 7.8
Interrupt Output
t2 t3 t1
IRQ/
CLK
7.4 PCI and External Memory Interface Timing Diagrams
Figure 7.9 through Figure 7.30 represent signal activity when the LSI53C875 accesses the PCI bus. The timings for the PCI and external memory buses are listed on page 7-50. This section includes timing diagrams for access to three groups of external memory configurations. The first group applies to systems with memory size of 64 Kbytes and above; one byte read or write cycle, and fast or normal ROMs. The second group applies to systems with memory size of 64 Kbytes and above, one byte read or write cycles, and slow ROMs. The third group applies to systems with memory size of 64 Kbytes or less, one byte read or write cycles, and normal or fast ROM. Note: Multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte.
PCI and External Memory Interface Timing Diagrams
7-13
Timing diagrams included in this section are:
*
Target Timing - - - - - - PCI Configuration Register Read PCI Configuration Register Write Operating Register/SCRIPTS RAM Read Operating Register/SCRIPTS RAM Write External Memory Read External Memory Write
*
Initiator Timing - - - - - - Opcode Fetch, Nonburst Burst Opcode Fetch Back-to-Back Read Back-to-Back Write Burst Read Burst Write
*
External Memory Timing - - - - - - - - - - Read Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access Write Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access Read Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access Write Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access Read Cycle, Slow Memory ( 64 Kbyte) Write Cycle, Slow Memory ( 64 Kbyte) Read Cycle, Normal/Fast Memory ( 64 Kbyte) Write Cycle, Normal/Fast Memory ( 64 Kbyte) Read Cycle, Slow Memory ( 64 Kbyte) Write Cycle, Slow Memory ( 64 Kbyte)
7-14
Instruction Set of the I/O Processor
7.4.1 Target Timing
Figure 7.9 through Figure 7.14 describe Target timing. Figure 7.9 PCI Configuration Register Read
CLK (Driven by System) t1 FRAME/ (Driven by System) AD/ (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) t3 DEVSEL/ (Driven by LSI53C875) t1 IDSEL (Driven by Master) t2 t1 Addr In t2 t3 Data Out t1 CMD t2 t1 In t2 t2 t2 Byte Enable t3 Out t2
t1 t3
PCI and External Memory Interface Timing Diagrams
7-15
Figure 7.10 PCI Configuration Register Write
CLK (Driven by System) t1 FRAME/ (Driven by Master) t1 AD/ (Driven by Master) t1 C_BE/ (Driven by Master) PAR (Driven by Master) t1 IRDY/ (Driven by Master) t3 TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) t3 DEVSEL/ (Driven by LSI53C875) t1 IDSEL (Driven by Master) t2 CMD t2 t1 t2 t2 t2 Byte Enable Addr In t2 t1 Data In t2 t2
7-16
Instruction Set of the I/O Processor
Figure 7.11 Operating Register/SCRIPTS RAM Read
CLK (Driven by System) t1 FRAME/ (Driven by Master) AD/ (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) t2 PAR (Driven by Master-Addr; LSI53C875-Data IRDY/ (Driven by Master) t3 TRDY/ (Driven by LSI53C875) t3 STOP/ (Driven by LSI53C875) t3 DEVSEL/ (Driven by LSI53C875) Addr In t1 t2 Byte Enable t1 In t1 t2 t2 t2 Out t3 t2 t3 Data Out t1 CMD
PCI and External Memory Interface Timing Diagrams
7-17
Figure 7.12 Operating Register/SCRIPTS RAM Write
CLK (Driven by System) t1 FRAME/ (Driven by Master) Addr In t1 AD/ (Driven by Master) t1 C_BE/ (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) t3 STOP/ (Driven by LSI53C875) t3 DEVSEL/ (Driven by LSI53C875) CMD t2 t1 t2 t1 t3 t2 t2 t2 Byte Enable t2 t1 t2 t1 Data In t2
7-18
Instruction Set of the I/O Processor
This page intentionally left blank.
PCI and External Memory Interface Timing Diagrams
7-19
Figure 7.13 External Memory Read
1 CLK (Driven by System) t1 FRAME/ (Driven by Master) t1 AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) t1 IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) MAD
(Addr Drvn by LSI53C875; Data Driven by Memory) Addr In
2
3
4
5
6
7
8
9
10
t2
t2
t1
CMD
t2 Byte Enable t1 t2
t3
GPIO_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
High Order Address t12 t11 t13
Middle Order Address
Low Order Address
t15
7-20
Instruction Set of the I/O Processor
Figure 7.13 External Memory Read (Cont.)
CLK (Driven by System) FRAME/ (Driven by Master) AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) t2 PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) t2 t3 Out 11 12 13 14 15 16 17 18 19 20 21
t3
Data Out
t3
t3
STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) t19 MAD
(Addr Drvn by LSI53C875; Data Driven by Memory)
t17 Data In
GPIO_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) t15 MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875) t16 t14
PCI and External Memory Interface Timing Diagrams
7-21
Figure 7.14 External Memory Write
1 CLK (Driven by System) t1 FRAME/ (Driven by Master) t1 AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) t3 DEVSEL/ (Driven by LSI53C875) MAD (Driven by LSI53C875) High Order Address t12 t11 t13 Middle Order Address Low Order Address
Addr In
2
3
4
5
6
7
8
9
10
t2
t1 Data In t2 Byte Enable t1 In t1 t2
t1
CMD
GPIO2_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
t20 t23
7-22
Instruction Set of the I/O Processor
Figure 7.14 External Memory Write (Cont.)
11 CLK (Driven by System) FRAME/ (Driven by Master) AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) t3 TRDY/ (Driven by LSI53C875) t3 STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) MAD (Driven by LSI53C875) GPIO2_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) t24 t25 t26 Data Out 12 13 14 15 16 17 18 19 20 21
t2
Data In
t2
Byte Enable t1 In t2
t2
t20 t23
t21 t22
MWE/ (Driven by LSI53C875)
PCI and External Memory Interface Timing Diagrams
7-23
7.4.2 Initiator Timing
Figure 7.17 through Figure 7.20 describe LSI53C875 Initiator timing. Figure 7.15 Opcode Fetch, Nonburst
CLK (Driven by System) t7 GPIO0_FETCH/
(Driven by LSI53C875)
t8
t9 GPIO1_MASTER/
(Driven by LSI53C875)
t10
t6 REQ/
(Driven by LSI53C875)
t4 GNT/ (Driven by Arbiter) t3 FRAME/
(Driven by LSI53C875)
t5
AD/ (Driven by LSI53C875-Addr; Target-Data) t3 C_BE/
(Driven by LSI53C875)
t1
Addr Out Addr Out
Data In CMD t3 t3 BE t1
Data In CMD BE
PAR/ (Driven by LSI53C875-Addr; Target-Data) IRDY/
(Driven by LSI53C875)
t3
t2
t1 TRDY/ (Driven by Target) STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target)
t2
t2
7-24
Instruction Set of the I/O Processor
Figure 7.16 Burst Opcode Fetch
CLK (Driven by System) t7 GPIO0_FETCH/
(Driven by LSI53C875)
t8
t9 GPIO1_MASTER/
(Driven by LSI53C875)
t10
t6 REQ/
(Driven by LSI53C875)
t4 GNT/ (Driven by Arbiter)
t5
t3 FRAME/
(Driven by LSI53C875)
AD/ (Driven by LSI53C875-Addr; Target-Data) C_BE/
(Driven by LSI53C875)
t3
Addr Out
t1
t2
t3 CMD t3 Out t3 t2 BE t1 In
Data In
PAR/ (Driven by LSI53C875-Addr; Target-Data) IRDY/
(Driven by LSI53C875)
In
t1 TRDY/ (Driven by Target)
t2
STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target) t2
PCI and External Memory Interface Timing Diagrams
7-25
Figure 7.17 Back-to-Back Read
CLK (Driven by System) GPIO0_FETCH/
(Driven by LSI53C875)
t9 GPIO1_MASTER/
(Driven by LSI53C875)
t10
t6 REQ/
(Driven by LSI53C875)
t4 GNT/ (Driven by Arbiter) t3 FRAME/
(Driven by LSI53C875)
t5
AD/ (Driven by LSI53C875-Addr; Target-Data) C_BE/
(Driven by LSI53C875)
t1
Addr Out
Addr Out t3
CMD
Data In t2 BE t1
CMD
Data In BE
PAR/ (Driven by LSI53C875-Addr; Target-Data) IRDY/
(Driven by LSI53C875)
t3 Out t3
In t2
Out
In
t2 t1 TRDY/ (Driven by Target) STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target) t2
7-26
Instruction Set of the I/O Processor
Figure 7.18 Back-to-Back Write
CLK (Driven by System) GPIO0_FETCH/
(Driven by LSI53C875)
t9 GPIO1_MASTER/
(Driven by LSI53C875)
t10
t6 REQ/
(Driven by LSI53C875)
t4 GNT/ (Driven by Arbiter) t3 FRAME/
(Driven by LSI53C875)
t5
t3 AD/
(Driven by LSI53C875) Addr Out Data Out Addr Out Data Out
t3 C_BE/
(Driven by LSI53C875)
t3 CMD BE t3 t3 CMD BE t3
PAR/
(Driven by LSI53C875)
t3 IRDY/
(Driven by LSI53C875)
t2
t2 t1 TRDY/ (Driven by Target)
STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target) t2
PCI and External Memory Interface Timing Diagrams
7-27
Figure 7.19 Burst Read
1 CLK 2 3 4 5 6 7 8 9
GPIO0_FETCH/
(Driven by LSI53C875)
t9 GPIO1_MASTER/
(Driven by LSI53C875)
t10
t6 REQ/
(Driven by LSI53C875)
t5 GNT/ (Driven by Arbiter)
t4
t3 FRAME/
(Driven by LSI53C875)
AD/
(Driven by LSI53C875-
t3 Addr Out t3
t2 Addr Out t3 CMD t3 Out t3 BE t2 In t1 Data In t3 CMD
Addr, Target-Data C_BE/
(Driven by LSI53C875)
PAR/
(Driven by LSI53C875)
for Address, by Target for Data) IRDY/
(Driven by LSI53C875)
TRDY/ (Driven by Target)
STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target) t2
7-28
Instruction Set of the I/O Processor
Figure 7.19 Burst Read (Cont.)
10 CLK 11 12 13 14 15 16 17 18 18 19
GPIO0_FETCH/
(Driven by LSI53C875)
GPIO1_MASTER/
(Driven by LSI53C875)
REQ/
(Driven by LSI53C875)
GNT/ (Driven by Arbiter)
FRAME/
(Driven by LSI53C875)
AD/
(Driven by LSI53C875-
Addr, Target-Data C_BE/
(Driven by LSI53C875)
Addr Out
BE
CMD
BE
PAR/
(Driven by LSI53C875)
for Address, by Target for Data) IRDY/
(Driven by LSI53C875)
In
In
Out
In
t1 TRDY/ (Driven by Target)
t2
STOP/ (Driven by Target) DEVSEL/ (Driven by Target)
PCI and External Memory Interface Timing Diagrams
7-29
Figure 7.20 Burst Write
1 CLK (Driven by System) GPIO0_FETCH/
(Driven by LSI53C875)
2
3
4
5
6
7
8
9
t9 GPIO1_MASTER/
(Driven by LSI53C875)
t10
t6 REQ/
(Driven by LSI53C875)
t4 GNT/ (Driven by Arbiter) FRAME/
(Driven by LSI53C875)
t5
t3
t3 AD/
(Driven by LSI53C875)
t3 Addr Out t3 CMD t3 Data Out Addr Out Data Out
t3 C_BE/
(Driven by LSI53C875)
BE
CMD t3
BE
PAR/
(Driven by LSI53C875)
t3 IRDY/
(Driven by LSI53C875)
t1 TRDY/ (Driven by Target)
STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target)
7-30
Instruction Set of the I/O Processor
Figure 7.20 Burst Write (Cont.)
10 CLK (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875) GPIO1_MASTER/ (Driven by LSI53C875) REQ/ (Driven by LSI53C875) 11 12 13 14 15 16 17 18
GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875)
AD/ Data (Driven by LSI53C875) Out C_BE/ (Driven by LSI53C875)
Addr Out
Data Out
CMD
BE
PAR/ (Driven by LSI53C875) IRDY/ (Driven by LSI53C875) t2 TRDY/ (Driven by Target)
STOP/ (Driven by Target) t2 DEVSEL/ (Driven by Target)
PCI and External Memory Interface Timing Diagrams
7-31
7.4.3 External Memory Timing
Figure 7.21 through Figure 7.30 describe LSI53C875 External Memory timing. Figure 7.21 Read Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access
1 CLK MAD
(Addr driven by LSI53C875;
2
3
4
5
6
7
8
9
Data driven by memory)
High Order Address t12 t11
Middle Order Address
Low Order Address
MAS2/ (Driven by LSI53C875) t13 MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) t14f MCE/ (Driven by LSI53C875) t13f MOE/ (Driven by LSI53C875)
t15f
MWE/ (Driven by LSI53C875)
7-32
Instruction Set of the I/O Processor
Figure 7.21 Read Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access (Cont.)
10 CLK t19 MAD
(Addr driven by LSI53C875; Valid Read Data
11
12
13
14
15
16
17
18
19
t17
Data driven by memory) MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) t14f MCE/ (Driven by LSI53C875) t16f MOE/ (Driven by LSI53C875)
t15f
t18
MWE/ (Driven by LSI53C875)
PCI and External Memory Interface Timing Diagrams
7-33
Figure 7.22 Write Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access
1 CLK MAD (Driven by LSI53C875) 2 3 4 5 6 7 8 9
High Order Address t11 t12
Middle Order Address
Low Order Address
Valid Write Data
MAS2/ (Driven by LSI53C875) t13 MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) t24 MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) t20 MWE/ (Driven by LSI53C875) t23
7-34
Instruction Set of the I/O Processor
Figure 7.22 Write Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte Access (Cont.)
10 CLK MAD (Driven by LSI53C875) 11 12 13 14 15 16 17 18 19
Valid Write Data
MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) t24f MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875) t22f t21
t26
t20 t23
PCI and External Memory Interface Timing Diagrams
7-35
Figure 7.23 Read Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access
1 CLK (Driven by System) FRAME/ (Driven by Master) AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) MAD
(Addr driven by LSI53C875) High Order Address
Middle Order Address
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Addr In
CMD Byte Enable
In
Data driven by memory) GPIO2_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) GPIO2_MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
Low Order Address
7-36
Instruction Set of the I/O Processor
Figure 7.23 Read Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access (Cont.)
17 CLK (Driven by System) FRAME/ (Driven by Master) AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) MAD
(Addr driven by LSI53C875)
Data In
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Data Out
Byte Enable
Out
Data driven by memory) GPIO2_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
Low Order Address
Data In
PCI and External Memory Interface Timing Diagrams
7-37
Figure 7.24 Write Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access
1 CLK (Driven by System) FRAME/ (Driven by Master) AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) MAD (Driven by LSI53C875) GPIO2_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
High Order Address
Middle Order Address
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Addr In Data In CMD Byte Enable
In
Low Order Address
Data Out
7-38
Instruction Set of the I/O Processor
Figure 7.24 Write Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte Access (Cont.)
17 CLK (Driven by System) FRAME/ (Driven by Master) AD (Driven by Master-Addr; LSI53C875-Data) C_BE/ (Driven by Master) PAR (Driven by Master-Addr; LSI53C875-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875) STOP/ (Driven by LSI53C875) DEVSEL/ (Driven by LSI53C875) MAD (Driven by LSI53C875) GPIO2_MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) MCE/ (Driven by LSI53C875) MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
Data Out
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Data In
Byte Enable
In
Low Order Address
PCI and External Memory Interface Timing Diagrams
7-39
Figure 7.25 Read Cycle, Slow Memory ( 64 Kbyte)
1 CLK MAD
(Address driven by LSI53C875 High Order Address
2
3
4
5
6
7
8
9
10
Data driven by memory) MAS2/ (Driven by LSI53C875)
Middle Address
Low order Address
t11
t12
t13 MAS1/ (Driven by LSI53C875) t15s MAS0/ (Driven by LSI53C875) t14s MCE/ (Driven by LSI53C875) t16s MOE/ (Driven by LSI53C875)
MWE/ (Driven by LSI53C875)
7-40
Instruction Set of the I/O Processor
Figure 7.25 Read Cycle, Slow Memory ( 64 Kbyte) (Cont.)
11 CLK MAD
(Address driven by LSI53C875
12
13
14
15
16
17
18
19
20
t17
Valid Read Data
Data driven by memory) MAS2/ (Driven by LSI53C875) t13 MAS1/ (Driven by LSI53C875) t15s MAS0/ (Driven by LSI53C875) t14s MCE/ (Driven byLSI53C875) t16s MOE/ (Driven by LSI53C875)
t19
t18
MWE/ (Driven by LSI53C875)
PCI and External Memory Interface Timing Diagrams
7-41
Figure 7.26 Write Cycle, Slow Memory ( 64 Kbyte)
1 CLK 2 3 4 5 6 7 8 9
MAD (Driven by LSI53C875) MAS2/ (Driven by LSI53C875)
High Order Address
Middle Address
Low order Address
Valid Write Data
t11
t12
t13 MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875) t24s MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) t20 MWE/ (Driven by LSI53C875) t23
7-42
Instruction Set of the I/O Processor
Figure 7.26 Write Cycle, Slow Memory ( 64 Kbyte) (Cont.)
10 CLK 11 12 13 14 15 16 17 18 19
MAD (Driven by LSI53C875)
Valid Write Data
MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875)
MAS0/ (Driven by LSI53C875) t24s MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) t26 t21 t20 t22s
MWE/ (Driven by LSI53C875) t23
PCI and External Memory Interface Timing Diagrams
7-43
Figure 7.27 Read Cycle, Normal/Fast Memory ( 64 Kbyte)
CLK MAD
(Addr driven by LSI53C875;
t19
High Order Address Low Order Address Valid Write Data
t17
Data driven by memory) MAS2/ (Driven by LSI53C875)
MAS1/ (Driven by LSI53C875) MAS0/ (Driven by LSI53C875)
t11
t12
t13
t15f
t14f MCE/ (Driven by LSI53C875) t16f MOE/ (Driven by LSI53C875) MWE/ (Driven by LSI53C875)
t18
7-44
Instruction Set of the I/O Processor
Figure 7.28 Write Cycle, Normal/Fast Memory ( 64 Kbyte)
CLK
MAD (Driven by LSI53C875) MAS2/ (Driven by LSI53C875)
High Order Address
Low Order Address
Valid Write Data
t11 MAS1/ (Driven by LSI53C875) t13 MAS0/ (Driven by LSI53C875)
t12
t24f MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) t23 MWE/ (Driven by LSI53C875) t26 t21 t22f
t20
PCI and External Memory Interface Timing Diagrams
7-45
Figure 7.29 Read Cycle, Slow Memory ( 64 Kbyte)
1 CLK MAD
(Address driven by LSI53C875
2
3
4
5
6
7
8
9
10
Data driven by memory) MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875)
High Order Address
Low order Address
t11 t13
t12
t15s MAS0/ (Driven by LSI53C875) t14s MCE/ (Driven by LSI53C875) t16s MOE/ (Driven by LSI53C875)
MWE/ (Driven by LSI53C875)
7-46
Instruction Set of the I/O Processor
Figure 7.29 Read Cycle, Slow Memory ( 64 Kbyte) (Cont.)
11 CLK t17 MAD
(Address driven by LSI53C875
Valid Read Data
12
13
14
15
16
17
18
19
20
Data driven by memory) MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875) t15s MAS0/ (Driven by LSI53C875) t14s MCE/ (Driven by LSI53C875) t16s MOE/ (Driven by LSI53C875)
t19
t18
MWE/ (Driven by LSI53C875)
PCI and External Memory Interface Timing Diagrams
7-47
Figure 7.30 Write Cycle, Slow Memory ( 64 Kbyte)
1 CLK 2 3 4 5 6 7 8 9
MAD (Driven by LSI53C875)
High Order Address
Low order Address
Valid Write Data
t12 MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875)
t11 t13
MAS0/ (Driven by LSI53C875) t24s MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) t20 t23 MWE/ (Driven by LSI53C875)
7-48
Instruction Set of the I/O Processor
Figure 7.30 Write Cycle, Slow Memory ( 64 Kbyte) (Cont.)
10 CLK 11 12 13 14 15 16 17 18 19
MAD (Driven by LSI53C875)
Valid Write Data
MAS2/ (Driven by LSI53C875) MAS1/ (Driven by LSI53C875)
MAS0/ (Driven by LSI53C875) t24s MCE/ (Driven by LSI53C875) t25 MOE/ (Driven by LSI53C875) t20 t23 MWE/ (Driven by LSI53C875) t22s t21 t26
PCI and External Memory Interface Timing Diagrams
7-49
7.5 PCI and External Memory Interface Timing
Table 7.19 lists the LSI53C875 PCI and External Memory Interface timing data.
Table 7.19
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14f t14s t15f t15s t16f t16s t17 t18 t19 t20 t21 t25 t26
LSI53C875 PCI and External Memory Interface Timing
Min 7 0 - 10 0 - - - - - 25 15 25 160 220 205 265 100 160 0 50 5 30 20 25 25 Max - - 11 - - 12 20 20 20 20 - - - - - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid Side signal input setup time Side signal input hold time CLK to side signal output valid CLK high to FETCH/ low CLK high to FETCH/ high CLK high to MASTER/ low CLK high to MASTER/ high Address setup to MAS/ high Address hold from MAS/ high MAS/ pulse width MCE/ low to data clocked in (fast memory) MCE/ low to data clocked in (slow memory) Address valid to data clocked in (fast memory) Address valid to data clocked in (slow memory) MOE/ low to data clocked in (fast memory) MOE/ low to data clocked in (slow memory) Data hold from address, MOE/, MCE/ change Next address out from MOE/, MCE/ high Data setup to CLK high Data setup to MWE/ low Data hold from MWE/ high MCE/ low to MWE/ low MWE/ high to MCE/ high
7-50
Instruction Set of the I/O Processor
7.6 SCSI Timing Diagrams
Table 7.20 through Table 7.29 and Figure 7.31 through Figure 7.35 describe the LSI53C875 SCSI timing.
Table 7.20
Symbol t1 t2 t3 t4
Initiator Asynchronous Send
Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SACK/ asserted Data hold from SREQ/ deasserted Min 5 5 55 20 Max - - - - Unit ns ns ns ns
Figure 7.31 Initiator Asynchronous Send
SREQ/ t1 SACK/ t3 SD[15:0]/ SDP[1:0]/ Valid n n t4 Valid n + 1 t2 n+1 n+1
SCSI Timing Diagrams
7-51
Table 7.21
Symbol t1 t2 t3 t4
Initiator Asynchronous Receive
Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Min 5 5 0 0 Max - - - - Unit ns ns ns ns
Figure 7.32 Initiator Asynchronous Receive
SREQ/ n t1 SACK/ t3 SD[15:0]/, SDP[1:0]/ Valid n n t4 Valid n + 1 t2 n+1 n+1
Table 7.22
Symbol t1 t2 t3 t4
Target Asynchronous Send
Parameter SREQ/ deasserted from SACK/ asserted SREQ/ asserted from SACK/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Min 5 5 55 20 Max - - - - Unit ns ns ns ns
Figure 7.33 Target Asynchronous Send
SREQ/ n+1
n t1
t2 n t4
SACK/ SD[15:0]/, SDP[1:0]/
t3
n+1
Valid n
Valid n + 1
7-52
Instruction Set of the I/O Processor
Table 7.23
Symbol t1 t2 t3 t4
Target Asynchronous Receive
Parameter SREQ/ deasserted from SACK/ asserted SREQ/ asserted from SACK/ deasserted Data setup to SACK/ asserted Data hold from SREQ/ deasserted Min 5 5 0 0 Max - - - - Unit ns ns ns ns
Figure 7.34 Target Asynchronous Receive
SREQ/ n t1 SACK/ t3 SD[15:0]/, SDP[1:0]/ Valid n n t4 Valid n + 1 t2 n+1 n+1
Figure 7.35 Initiator and Target Synchronous Transfer
t1 SREQ/ or SACK/ t3 Send Data SD[15:0]/, SDP[1:0]/ t5 Receive Data SD[15:0]/, SDP[1:0]/ n t4 Valid n t6 Valid n Valid n + 1 Valid n + 1 t2 n+1
SCSI Timing Diagrams
7-53
Table 7.24
Symbol t1 t2 t1 t2 t3 t4 t5 t6
SCSI-1 Transfers (SE, 5.0 Mbytes/s)
Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted Min 90 90 90 90 55 100 0 45 Max - - - - - - - - Unit ns ns ns ns ns ns ns ns
Table 7.25
Symbol t1 t2 t1 t2 t3 t4 t5 t6
SCSI-1 Transfers (Differential, 4.17 Mbytes/s)
Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted Min 96 96 84 84 65 110 0 45 Max - - - - - - - - Unit ns ns ns ns ns ns ns ns
7-54
Instruction Set of the I/O Processor
Table 7.26
SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock
Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted Min 35 35 20 20 33 40 0 10 Max - - - - - - - - Unit ns ns ns ns ns ns ns ns
Symbol t1 t2 t1 t2 t3 t4 t5 t6
Table 7.27
SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers), 50 MHz Clock
Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted Min 35 35 20 20 33 401 0 10 Max - - - - - - - - Unit ns ns ns ns ns ns ns ns
Symbol t1 t2 t1 t2 t3 t4 t5 t6
1. Analysis of system configuration is recommended due to reduced driver skew margin in differential systems. Notes: Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1)) is set. For Fast SCSI, set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3)).
SCSI Timing Diagrams
7-55
Table 7.28
Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock
Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted Min 16 16 10 10 12 17 0 6 Max - - - - - - - - Unit ns ns ns ns ns ns ns ns
Symbol t1 t2 t1 t2 t3 t4 t5 t6
Notes: Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1)) is set. For Fast SCSI, set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3)). During Ultra SCSI transfers, the value of the Extend REQ/ ACK Filtering bit (SCSI Test Two (STEST2), bit 1) has no effect.
7-56
Instruction Set of the I/O Processor
Table 7.29
Ultra SCSI Differential Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock
Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted Min 16 16 10 10 16 21 0 6 Max - - - - - - - - Unit ns ns ns ns ns ns ns ns
Symbol t1 t2 t1 t2 t3 t4 t5 t6
Notes: Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1)) is set. For Fast SCSI, set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3)). During Ultra SCSI transfers, the value of the Extend REQ/ ACK Filtering bit (SCSI Test Two (STEST2), bit 1) has no effect.
SCSI Timing Diagrams
7-57
7.7 Package Drawings
Figure 7.36 is the 169-pin PBGA mechanical drawing and Figure 7.37 is the 160-pin PQFP mechanical drawing for the LSI53C875. Figure 7.36 169-Pin PBGA (GV) Mechanical Drawing
Important:
This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code GV.
7-58
Instruction Set of the I/O Processor
Figure 7.37 160-pin PQFP (P3) Mechanical Drawing (Sheet 1 of 2)
Important:
This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P3.
Package Drawings
7-59
Figure 7.37 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2)
Important:
This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P3.
7-60
Instruction Set of the I/O Processor
Appendix A Register Summary
Table A.1 lists the LSI53C875 configuration registers by register name. Table A.1 Configuration Registers
Address 0x14 0x10 0x46 0x0C 0x34 0x40 0x09 0x04 0x47 0x02 0x30 0x0E 0x3C 0x3D 0x0D 0x3F 0x3E 0x41 Read/Write Page Read/Write Read/Write Read Only Read/Write Read Only Read Only Read Only Read/Write Read Only Read Only Read/Write Read Only Read/Write Read Only Read/Write Read Only Read Only Read Only 3-19 3-19 3-27 3-18 3-22 3-25 3-17 3-13 3-28 3-13 3-21 3-19 3-23 3-23 3-18 3-24 3-24 3-25
Register Name Base Address One (Memory) Base Address Zero (I/O) Bridge Support Extensions (PMCSR_BSE) Cache Line Size Capabilities Pointer Capability ID Class Code Command Data Device ID Expansion ROM Base Address Header Type Interrupt Line Interrupt Pin Latency Timer Max_Lat Min_Gnt Next Item Pointer
LSI53C875/875E PCI to Ultra SCSI I/O Processor
A-1
Table A.1
Configuration Registers (Cont.)
Address 0x42 0x44 0x18 0x08 0x06 0x2E 0x2C 0x00 Read/Write Page Read Only Read/Write Read/Write Read Only Read/Write Read Only Read Only Read Only 3-25 3-26 3-20 3-17 3-15 3-21 3-20 3-13
Register Name Power Management Capabilities Power Management Control/Status RAM Base Address Two (Memory) SCRIPTS RAM Revision ID Status Subsystem ID (SSID) Subsystem Vendor ID (SSVID) Vendor ID
Table A.2 lists the LSI53C875 operating registers by register name. Table A.2 LSI53C875 Register Map
Address (Memory or I/O) (Config. Memory or I/O) Read/Write Page 0x3C-0x3F (0xBC-0xBF) 0x22 (0xA2) 0x21 (0xA1) 0x19 (0x99) 0x23 (0xA3) 0x1B (0x9B) 0x1A (0x9A) 0x18 (0x98) 0x10-0x13 (0x90-0x93) 0x24-0x26 (0xA4-0xA6) 0x27 (0xA7) 0x3B (0xBB) 0x20 (0xA0) Read Only Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 5-53 5-42 5-40 5-35 5-43 5-37 5-35 5-34 5-31 5-44 5-45 5-51 5-39
Register Name Adder Sum Output (ADDER) Chip Test Five (CTEST5) Chip Test Four (CTEST4) Chip Test One (CTEST1) Chip Test Six (CTEST6) Chip Test Three (CTEST3) Chip Test Two (CTEST2) Chip Test Zero (CTEST0) Data Structure Address (DSA) DMA Byte Counter (DBC) DMA Command (DCMD) DMA Control (DCNTL) DMA FIFO (DFIFO)
A-2
Register Summary
Table A.2
LSI53C875 Register Map (Cont.)
Address (Memory or I/O) (Config. Memory or I/O) Read/Write Page 0x39 (0xB9) 0x38 (0xB8) 0x28-0x2B (0xA8-0xAB) 0x2C-0x2F (0xAC-0xAF) 0x30-0x33 (0xB0-0xB3) 0x0C (0x8C) 0x07 (0x87) 0x47 (0xC7) 0x14 (0x94) Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read Only Read/Write Read/Write Read/Write Read/Write Read/Write 5-50 5-47 5-45 5-46 5-46 5-23 5-19 5-63 5-31 5-62 5-70 5-69 5-51 5-47 5-79 5-79 5-22 5-78 5-14 5-6 5-12 5-9 5-3
Register Name DMA Interrupt Enable (DIEN) DMA Mode (DMODE) DMA Next Address (DNAD) DMA SCRIPTS Pointer (DSP) DMA SCRIPTS Pointer Save (DSPS) DMA Status (DSTAT) General Purpose (GPREG) General Purpose Pin Control (GPCNTL) Interrupt Status (ISTAT)
Memory Access Control (MACNTL) 0x46 (0xC6) Response ID One (RESPID1) Response ID Zero (RESPID0) Scratch Byte Register (SBR) Scratch Register A (SCRATCHA) Scratch Register B (SCRATCHB) Scratch Registers C-J (SCRATCHC-SCRATCHJ) SCSI Bus Control Lines (SBCL) SCSI Bus Data Lines (SBDL) SCSI Chip ID (SCID) SCSI Control One (SCNTL1) SCSI Control Three (SCNTL3) SCSI Control Two (SCNTL2) SCSI Control Zero (SCNTL0) 0x4B (0xCB) 0x4A (0xCA) 0x3A (0xBA) 0x34-0x37 (0xB4-0xB7) 0x5C-0x5F (0xDC-0xDF) 0x60-0x7F (0xE0-0xFF) 0x0B (0x8B) 0x58-0x59 (0xD8-0xD9) 0x04 (0x84) 0x01 (0x81) 0x03 (0x83) 0x02 (0x82) 0x00 (0x80)
Register Summary
A-3
Table A.2
LSI53C875 Register Map (Cont.)
Address (Memory or I/O) (Config. Memory or I/O) Read/Write Page 0x06 (0x86) 0x08 (0x88) 0x50-0x51 (0xD0-0xD1) Read/Write Read/Write Read Only Read/Write Read/Write Read Only Read Only Read/Write Read/Write Read/Write Read Only Read Only Read Only Read Only Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write 5-18 5-20 5-77 5-55 5-53 5-59 5-56 5-60 5-21 5-78 5-22 5-27 5-29 5-26 5-72 5-75 5-73 5-70 5-66 5-64 5-15 5-61 5-38
Register Name SCSI Destination ID (SDID) SCSI First Byte Received (SFBR) SCSI Input Data Latch (SIDL)
SCSI Interrupt Enable One (SIEN1) 0x41 (0xC1) SCSI Interrupt Enable Zero (SIEN0) 0x40 (0xC0) SCSI Interrupt Status One (SIST1) 0x43 (0xC3)
SCSI Interrupt Status Zero (SIST0) 0x42 (0xC2) SCSI Longitudinal Parity (SLPAR) 0x44 (0xC4)
SCSI Output Control Latch (SOCL) 0x09 (0x89) SCSI Output Data Latch (SODL) SCSI Selector ID (SSID) SCSI Status One (SSTAT1) SCSI Status Two (SSTAT2) SCSI Status Zero (SSTAT0) SCSI Test One (STEST1) SCSI Test Three (STEST3) SCSI Test Two (STEST2) SCSI Test Zero (STEST0) SCSI Timer One (STIME1) SCSI Timer Zero (STIME0) SCSI Transfer (SXFER) SCSI Wide Residue (SWIDE) Temporary (TEMP) 0x54-0x55 (0xD4-0xD5) 0x0A (0x09) 0x0E (0x8E) 0x0F (0x8F) 0x0D (0x8D) 0x4D (0xCD) 0x4F (0xCF) 0x4E (0xCE) 0x4C (0xCC) 0x49 (0xC9) 0x48 (0xC8) 0x05 (0x85) 0x45 (0xC5) 0x1C-0x1F (0x9C-0x9F)
A-4
Register Summary
Appendix B External Memory Interface Diagram Examples
Figure B.1 64 Kbyte Interface with 200 ns Memory
MOE/ OE MCE/ CE MAD0 MAD1 MAD2 MAD3 4.7 K 4.7 K 4.7 K 4.7 K VSS A[13:8] 27C128 D[7:0] A[7:0]
MAD[7:0] Bus
LSI53C875 MAS0/
8 D0 Q0 HCT374 D7 Q7 CK 0E
8
6 MAS1/
D0 Q0 6 HCT374 D5 Q5 CK 0E
Note: MAD bus sense logic enabled for 16 Kbytes of slow memory (200 ns device @ 33 MHz).
LSI53C875/875E PCI to Ultra SCSI I/O Processor
B-1
Figure B.2
64 Kbyte Interface with 150 ns Memory
Optional - for Flash Memory only, not required for EEPROMS.
+ 12 V GPIO4 MWE/ MOE/ VPP Control
VPP
WE OE
MCE/
CE MAD1 MAD3 4.7 K 4.7 K A[15:8] VSS D[7:0] 27C512-15/ 28F512-15/ Socket
MAD[7:0] Bus
A[7:0]
LSI53C875 8 MAS0/ D0 Q0 HCT374 D7 Q7 CK 0E 8
8 MAS1/
D0 Q0 8 HCT374 D7 Q7 CK 0E
Note: MAD bus sense logic enabled for 64 Kbytes of fast memory (150 ns device @ 33 MHz).
B-2
External Memory Interface Diagram Examples
Figure B.3
256 Kbyte Interface with 150 ns Memory
Optional - for Flash Memory only, not required for EEPROMS.
+ 12 V GPIO4 MWE/ MOE/ VPP Control
VPP
WE OE
MCE/
CE MAD1 MAD2 4.7 K 4.7 K A[15:8] VSS A[17:16] 27C020-15/ 28F020-15/ Socket D[7:0]
MAD[7:0] Bus
A[7:0]
LSI53C875 8 D0 Q0 HCT374 D7 Q7 CK 0E 8
MAS0/
8 MAS1/
D0 Q0 HCT374 D7 Q7 CK 0E
8
2 MAD[1:0] Bus
D0 Q0 HCT377 D1 Q1 CK 0E
2
Note: MAD bus sense logic enabled for 256 Kbytes of fast memory (150 ns device @ 33 MHz). The HCT374s may be replaced with HCT377s.
External Memory Interface Diagram Examples
B-3
Figure B.4
512 Kbyte Interface with 150 ns Memory
Optional - for Flash Memory only, not required for EEPROMS. 27C010-15/28F010-15 Sockets + 12 V GPIO4 MWE/ MOE/ OE D0 D[7:0] D7 A[7:0] A0 A[15:8] OE D0 D7 A0 OE D0 D7 A0 OE D0 D7 A0 VPP Control VPP
MAD[7:0] Bus
MAD0 MAD2
4.7 K 4.7 K
VSS
LSI53C875 MAS0/
8 D0 Q0 HCT374 D7 Q7 CK 0E
8
MAS1/
D0 Q0 8 8 HCT374 D7 Q7 CK 0E
A16
A16 CE
A16 CE
A16 CE
A16 CE
MCE/
D0 Q0 3 HCT377 MAD[2:0] Bus D2 Q2 CK 0E
A17 A18
A B GB
Y0 Y1 Y2 Y3
HCT139 Note: MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns devices, additional time required for HCT139 @ 33 MHz). The HCT374s may be replaced with HCT377s.
B-4
External Memory Interface Diagram Examples
Index
Numerics
3.3/5 volt PCI interface 2-9 3-state 4-6
C
cache line size enable bit 5-51 cache mode, see PCI cache mode 3-4 chained block moves 2-34 to 2-38 SODL register 2-36 SWIDE register 2-36 wide SCSI receive bit 2-36 wide SCSI send bit 2-35 chained mode bit 5-9 chip revision level bits 5-37 chip test five register 5-42 chip test four register 5-40 chip test one register 5-35 chip test six register 5-43 chip test two register 5-35 chip test zero register 5-34 chip type bits 5-62 clear DMA FIFO bit 5-37 clear SCSI FIFO bit 5-76 clock address incrementor bit 5-42 clock byte counter bit 5-42 clock conversion factor bits 5-13 configuration registers. See PCI configuration registers configured as I/O bit 5-36 configured as memory bit 5-36 connected bit 5-7, 5-33 CTEST0 register 5-34 CTEST1 register 5-35 CTEST2 register 5-35 CTEST4 register 5-40 CTEST5 register 5-42 CTEST6 register 5-43
A
abort operation bit 5-31 aborted bit 5-24, 5-50 active negation see TolerANT technology active termination 2-23 adder register 5-53 adder sum output register 5-53 always wide SCSI bit 5-74 arbitration arbitration in progress bit 5-27 arbitration mode bits 5-3 immediate arbitration bit 5-8 in progress bit 5-27 lost arbitration bit 5-27 mode bits 5-3 priority encoder test bit 5-71 won arbitration bit 5-27 assert even SCSI parity bit 5-7 assert SATN/ on parity error bit 5-5 assert SCSI ACK/ signal bit 5-21 assert SCSI ATN/ signal bit 5-21 assert SCSI BSY/ signal bit 5-21 assert SCSI C_D/ signal bit 5-21 assert SCSI data bus bit 5-6 assert SCSI I_O signal bits 5-21 assert SCSI MSG/ signal bit 5-21 assert SCSI REQ/ signal bit 5-21 assert SCSI RST/ signal bit 5-7 assert SCSI SEL/ signal bit 5-21
D
data acknowledge status bit 5-37 data path 2-16 data request status bit 5-37 data structure address register 5-31 data transfer direction bit 5-35 dataRD bit 5-62 dataWR bit 5-62 DBC register 5-44 DBLEN bit 3 5-72 DBLSEL bit 2 5-72 DCMD register 5-45 DCNTL register 5-51 destination I/O memory enable bit 5-48 DFIFO register 5-39 DIEN register 5-50
B
bidirectional 4-6 big and little endian support 2-10 block move instructions 6-5 burst disable bit 5-40 burst length bits 5-43, 5-47 burst opcode fetch enable bit 5-49 bus fault bit 5-24, 5-50 byte empty in DMA FIFO (FMT) 5-34 byte empty in DMA FIFO bit 5-35 byte full in DMA FIFO bit 5-35 byte offset counter bits 5-39, 5-43
LSI53C875/875E PCI to Ultra SCSI I/O Processor
IX-1
DIF bit 5-73 differential mode DIFFSENS 4-19 direction control pins 4-16 operation 2-20 SCSI differential mode bit 5-73 DIFFSENS SCSI signal 7-3 disable halt on parity error or ATN 5-7 disable single initiator response bit 5-76 DMA byte counter register 5-44 DMA command register 5-45 DMA control register 5-51 DMA core 2-2 DMA direction bit 5-42 DMA FIFO bits 5-43 DMA FIFO empty bit 5-23 DMA FIFO register 5-39 DMA FIFO size bit 5-42 DMA interrupt enable register 5-50 DMA interrupt pending bit 5-34 DMA mode register 5-47 DMA next address register 5-45 DMA SCRIPTS pointer register 5-46 DMA SCRIPTS pointer save register 5-46 DMA status register 5-23 DMODE register 5-47 DNAD register 5-45 DSA register 5-31 DSP register 5-46 DSPS register 5-46 DSTAT register 5-23
G
general purpose pin control register 5-63 general purpose register 5-19 general purpose timer expired bit 5-56, 5-59 general purpose timer period bits 5-68 general purpose timer scale factor bit 5-66 GPCNTL register 5-63 GPIO enable bit 5-63 GPIO[4:0] bits 5-19 GPREG register 5-19
H
halt SCSI clock bit 5-76 handshake-to-handshake timer bus activity enable bit 5-66 handshake-to-handshake timer expired bit 5-56, 5-59 handshake-to-handshake timer period bit 5-64 high impedance mode bit 5-40
I
I/O instructions 6-12 illegal instruction detected bit 5-24 immediate arbitration bit 5-8 input 4-6 instruction prefetching 2-5 prefetch enable bit 5-51 prefetch flush bit 5-51 prefetch unit flushing 2-5 instructions block move 6-5 I/O 6-12 load and store 6-37 memory move 6-33 read/write 6-21 transfer control 6-26 internal RAM, see also SCRIPTS RAM 2-3 interrupt status register 5-31 interrupt-on-the-fly bit 5-33 interrupts fatal vs. nonfatal interrupts 2-30 halting 2-33 IRQ disable bit 2-30 masking 2-31 sample interrupt service routine 2-33 stacked interrupts 2-32 IRQ disable bit 5-52 IRQ mode bit 5-52 ISTAT register 5-31
E
enable parity checking bit 5-5 enable read line bit 5-49 enable read multiple bit 5-49 enable response to reselection bit 5-14 enable response to selection bit 5-14 enable wide SCSI bit 5-12 encoded chip SCSI ID 5-14 encoded destination SCSI ID bit 5-22 encoded destination SCSI ID bits 5-18 extend SREQ/SACK filtering bit 5-74 external memory interface 2-6, 2-7 configuration 2-7 flash ROM updates 2-6 GPIO4 bit 5-19 multiple byte accesses 7-13 slow memory 2-8 system requirements 2-6 extra clock cycle of data setup bit 5-6
J
JTAG support 2-10
F
fetch enable 5-63 fetch pin mode bit 5-38 FIFO byte control bits 5-41 FIFO flags bits 5-27, 5-30 flush DMA FIFO bit 5-37 FMT 5-34 function complete bit 5-54, 5-57
L
last disconnect bit 5-30 latched SCSI parity bit 5-28 latched SCSI parity for SD[15:8] bit 5-30 load and store instructions 6-37 no flush option 6-38 prefetch unit and store instructions 2-6, 6-38 lost arbitration bit 5-27 LSI53C700 family compatibility bit 5-53
IX-2
Index
M
MACNTL register 5-62 MAD bus programming 4-22 MAD[0] 4-24 MAD[3:1] 4-24 MAD[4] 4-23 MAD[5] 4-23 MAD[6] 4-23 MAD[7] 4-22 manual start mode bit 5-49 master control for set or reset pulses bit 5-42 master data parity error bit 5-24, 5-50 master enable bit 5-63 master parity error enable bit 5-41 max SCSI synchronous offset bits 5-17 memory access control register 5-62 memory move instructions 6-33 and SCRIPTS instruction prefetching 2-5 no flush option 2-5 memory read line command 3-8 memory read multiple command 3-9 memory write and invalidate command 3-6 write and invalidate mode bit 3-14 MG[7:0] 3-24 min_gnt (MG[7:0]) 3-24
N
no flush memory move instruction 6-34
SCSI bus data lines 5-78 SCSI chip ID 5-14 SCSI control one register 5-6 SCSI control register two 5-9 SCSI control three 5-12 SCSI control zero 5-3 SCSI destination ID 5-18 SCSI first byte received 5-20 SCSI input data latch 5-77 SCSI interrupt enable one 5-55 SCSI interrupt enable zero 5-53 SCSI interrupt status one 5-59 SCSI interrupt status zero 5-56 SCSI longitudinal parity 5-60 SCSI output control latch 5-21 SCSI output data latch 5-78 SCSI selector ID 5-22 SCSI status one 5-27 SCSI status two 5-29 SCSI status zero 5-26 SCSI test one 5-72 SCSI test three 5-75 SCSI test two 5-73 SCSI test zero 5-70 SCSI timer one 5-66 SCSI timer zero 5-64 SCSI transfer 5-15 SCSI wide residue 5-61 temporary stack 5-38
P
package and feature options 1-4 parity 2-12 parity error bit 5-58 PCI cache mode 3-4 cache line size enable bit 5-51 cache line size register 3-18 enable read multiple bit 5-49 memory read line command 3-8 memory read multiple command 3-9 memory write and invalidate command 3-6 write and invalidate mode bit 3-14 write and invalidate enable bit 5-38 PCI commands 3-2 PCI configuration registers 3-11 to 3-24 base address one (memory) 3-19 base address zero (I/O) 3-19 cache line size 3-18 class code 3-17 command 3-13 data 3-28 device ID 3-13 expansion ROM base address 3-21 header type 3-19 interrupt line 3-23 interrupt pin 3-23 latency timer 3-18 max_lat 3-24 min_gnt 3-24 next item pointer 3-25 power management control/status 3-26 revision ID 3-17 status 3-15 subsystem data 3-20 subsystem ID (SSID) 3-21
O
opcode fetch bursting 2-6 operating registers adder sum output 5-53 chip test five 5-42 chip test four 5-40 chip test one 5-35 chip test six 5-43 chip test three 5-37 chip test two 5-35 chip test zero 5-34 data structure address 5-31 DMA byte counter 5-44 DMA command 5-45 DMA control 5-51 DMA FIFO 5-39 DMA interrupt enable 5-50 DMA mode 5-47 DMA next address 5-45 DMA SCRIPTS pointer 5-46 DMA SCRIPTS pointer save 5-46 DMA status 5-23 general information 5-1 general purpose 5-19 general purpose pin control 5-63 interrupt status 5-31 memory access control 5-62 response ID one 5-70 response ID zero 5-69 scratch byte 5-51 scratch register A 5-47 scratch register B 5-79 SCSI bus control Lines 5-22
Index
IX-3
subsystem vendor ID (SSVID) 3-20 vendor ID 3-13 PCI configuration space 3-1 PCI I/O space 3-2 PCI memory space 3-2 PCI timings 7-50 phase mismatch bit 5-57 pointer SCRIPTS bit 5-62 power management power state D0 2-38 power state D3 2-39 prefetch enable bit 5-51 prefetch flush bit 5-51
R
RAM, see also SCRIPTS RAM 2-3 read/write instructions 6-21 register addresses operating registers 0x00 5-3 0x01 5-6 0x02 5-9 0x03 5-12 0x04 5-14 0x05 5-15 0x06 5-18 0x07 5-19 0x08 5-20 0x09 5-21 0x0A 5-22 0x0B 5-22 0x0C 5-23 0x0D 5-26 0x0E 5-27 0x0F 5-29 0x10-0x13 5-31 0x14 5-31 0x18 5-34 0x19 5-35 0x1A 5-35 0x1B 5-37 0x1C-0x1F 5-38 0x20 5-39 0x21 5-40 0x22 5-42 0x23 5-43 0x24-0x26 5-44 0x27 5-45 0x28-0x2B 5-45 0x2C-0x2F 5-46 0x30-0x33 5-46 0x34-0x37 5-47 0x38 5-47 0x39 5-50 0x3A 5-51 0x3B 5-51 0x3C-0x3F 5-53 0x40 5-53 0x41 5-55 0x42 5-56 0x43 5-59 0x44 5-60 0x45 5-61 0x46 5-62 0x47 5-63
0x48 5-64 0x49 5-66 0x4A 5-69 0x4B 5-70 0x4C 5-70 0x4D 5-72 0x4E 5-73 0x4F 5-75 0x50-0x51 5-77 0x54-0x55 5-78 0x58-0x59 5-78 0x5C-0x5F 5-79 0x60-0x70 5-79 PCI configuration registers 0x00 3-13 0x02 3-13 0x04 3-13 0x06 3-15 0x08 3-17 0x0C 3-18 0x0D 3-18 0x0E 3-19 0x10 3-19 0x14 3-19 0x18 3-20 0x2C 3-20 0x2E 3-21 0x30 3-21 0x34 3-22 0x3C 3-23 0x3D 3-23 0x3E 3-24 0x3F 3-24 0x40 3-25 0x41 3-25 0x42 3-25 0x44 3-26 0x46 3-27 0x47 3-28 subsystem data 3-20 register bits abort operation 5-31 aborted 5-24, 5-50 always wide SCSI 5-74 arbitration priority encoder test 5-71 arbitration in progress 5-27 arbitration mode 5-3 assert even SCSI parity (force bad parity)) 5-7 assert SATN/ on parity error 5-5 assert SCSI ACK/ signal 5-21 assert SCSI ATN/ signal 5-21 assert SCSI BSY/ signal 5-21 assert SCSI C_D/ signal 5-21 assert SCSI data bus 5-6 assert SCSI I_O/ signal 5-21 assert SCSI MSG/ signal 5-21 assert SCSI REQ/ signal 5-21 assert SCSI RST/ signal 5-7 assert SCSI SEL/ signal 5-21 burst disable 5-40 burst length 5-43, 5-47 burst opcode fetch enable 5-49 bus fault 5-24, 5-50 byte empty in DMA FIFO 5-35 byte full in DMA FIFO 5-35
IX-4
Index
byte offset counter 5-39, 5-43 cache line size enable 5-51 chained mode 5-9 chip revision level 5-37 chip type 5-62 clear DMA FIFO 5-37 clear SCSI FIFO 5-76 clock address incrementor 5-42 clock byte counter 5-42 clock conversion factor 5-13 configured as I/O 5-36 configured as memory 5-36 connected 5-7, 5-33 data acknowledge status 5-37 data request status 5-37 data transfer direction 5-35 dataRD 5-62 dataWR 5-62 destination I/O memory enable 5-48 disable halt on parity error or ATN 5-7 disable single initiator response 5-76 DMA direction 5-42 DMA FIFO 5-43 DMA FIFO empty 5-23 DMA FIFO size 5-42 DMA interrupt pending 5-34 enable parity checking 5-5 enable read line 5-49 enable read multiple 5-49 enable response to reselection 5-14 enable response to selection 5-14 enable wide SCSI 5-12 encoded chip SCSI ID, bits [3:0] 5-14 encoded destination SCSI ID 5-18, 5-22 extend SREQ/SACK filtering 5-74 extra clock cycle of data setup 5-6 fetch enable 5-63 fetch pin mode 5-38 FIFO byte control 5-41 FIFO flags 5-27, 5-30 flush DMA FIFO 5-37 function complete 5-54, 5-57 general purpose timer expired 5-56, 5-59 general purpose timer period 5-68 general purpose timer scale factor 5-66 GPIO enable 5-63 GPIO[4:0] 5-19 halt SCSI clock 5-76 handshake-to-handshake timer bus activity enable 5-66 handshake-to-handshake timer expired 5-56, 5-59 handshake-to-handshake timer period 5-64 high impedance mode 5-40 illegal instruction detected 5-24, 5-50 immediate arbitration 5-8 interrupt-on-the-fly 5-33 IRQ disable 5-52 IRQ mode 5-52 last disconnect 5-30 latched SCSI parity 5-28 latched SCSI parity for SD[15:8] 5-30 lost arbitration 5-27 LSI53C700 family compatibility 5-53 manual start mode 5-49 master control for set or reset pulses 5-42 master data parity error 5-24, 5-50 master enable 5-63
master parity error enable 5-41 max SCSI synchronous offset 5-17 parity error 5-58 phase mismatch 5-57 pointer SCRIPTS 5-62 prefetch enable 5-51 prefetch flush 5-51 reselected 5-54, 5-57 reset SCSI offset 5-73 SACK/ status 5-22 SATN/ status 5-22 SBSY/ status 5-22 SC_D/ status 5-23 SCLK 5-72 SCLK doubler enable bit 5-72 SCLK doubler select bit 5-72 scratchA/B operation 5-36 SCRIPTS 5-62 SCRIPTS interrupt instruction received 5-24, 5-50 SCSI C_D/ signal 5-28 SCSI control enable 5-73 SCSI data high impedance 5-40 SCSI differential mode 5-73 SCSI disconnect unexpected 5-9 SCSI FIFO test read 5-75 SCSI FIFO test write 5-77 SCSI gross error 5-54, 5-57 SCSI high impedance mode 5-74 SCSI I_O/ signal 5-28 SCSI interrupt pending 5-33 SCSI isolation mode 5-72 SCSI loopback mode 5-74 SCSI low level mode 5-74 SCSI MSG/ signal 5-28 SCSI parity error 5-55 SCSI phase mismatch - initiator mode 5-54 SCSI reset condition 5-55 SCSI RST/ received 5-58 SCSI RST/ signal 5-27 SCSI SDP0/ parity signal 5-27 SCSI SDP1 signal 5-30 SCSI selected as ID 5-70 SCSI synchronous offset maximum 5-71 SCSI synchronous offset zero 5-71 SCSI synchronous transfer period 5-15 SCSI true end of process 5-36 SCSI valid 5-22 select with SATN/ on a start sequence 5-4 selected 5-54, 5-57 selection or reselection time-out 5-56, 5-59 selection response logic test 5-71 selection time-out 5-65 semaphore 5-32 shadow register test mode 5-40 SI_O/ status 5-23 SIDL least significant byte full 5-26 SIDL most significant byte full 5-29 signal process 5-32, 5-36 single step interrupt 5-24, 5-50 single step mode 5-51 SLPAR high byte enable 5-10 SLPAR mode 5-10 SMSG/ status 5-23 SODL least significant byte full 5-26 SODL most significant byte full 5-29 SODR least significant byte full 5-26
Index
IX-5
SODR most significant byte full 5-29 software reset 5-32 source I/O memory enable 5-48 SREQ/ status 5-22 SSEL/ status 5-22 start DMA operation 5-52 start SCSI transfer 5-8 start sequence 5-4 synchronous clock conversion factor 5-12 target mode 5-6 timer test mode 5-76 TolerANT enable 5-75 Ultra enable 5-12 unexpected disconnect 5-55, 5-58 wide SCSI receive 5-11 wide SCSI send 5-10 won arbitration 5-27 write and invalidate enable 5-38 reselected bit 5-54, 5-57 reset SCSI offset bit 5-73 RESPID0 register 5-69 RESPID1 register 5-70 response ID one register 5-70 response ID zero register 5-69 revision level bits 5-37
S
SACK/ status bit 5-22 SATN/ active 5-57 SATN/ active bit 5-57 SATN/ status bit 5-22 SBCL register 5-22 SBDL register 5-78 SBR register 5-51 SBSY status bit 5-22 SC_D/ status bit 5-23 SCID register 5-14 SCLK bit 5-72 SCNTL0 register 5-3 SCNTL1 register 5-6 SCNTL2 register 5-9 SCNTL3 register 5-12 scratch register 5-51 scratchA register 5-47 scratchA/B operation bit 5-36 scratchB register 5-79 SCRIPTS bit 5-62 SCRIPTS interrupt instruction received bit 5-24 SCRIPTS processor 2-2 instruction prefetching 2-5 internal RAM for instruction storage 2-3 performance 2-2 SCRIPTS RAM 2-3 scratchA/B operation bit 5-36 SCSI core 2-1 differential mode 2-20 termination 2-23 timings 7-51 TolerANT technology 1-5 SCSI ATN condition - target mode 5-54 SCSI ATN condition bit 5-54 SCSI bus control lines register 5-22 SCSI bus data lines register 5-78 SCSI bus interface 2-19 to 2-25
SCSI C_D/ signal bit 5-28 SCSI chip ID register 5-14 SCSI control enable bit 5-73 SCSI control one register 5-6 SCSI control three register 5-12 SCSI control two register 5-9 SCSI control zero register 5-3 SCSI core 2-1 SCSI data high impedance bit 5-40 SCSI destination ID register 5-18 SCSI differential mode bit 5-73 SCSI disconnect unexpected bit 5-9 SCSI FIFO test read bit 5-75 SCSI FIFO test write bit 5-77 SCSI first byte received register 5-20 SCSI gross error bit 5-54, 5-57 SCSI high impedance mode bit 5-74 SCSI I_O/ signal bit 5-28 SCSI input data latch register 5-77 SCSI instructions block move 6-5 I/O 6-12 load/store 6-37 memory move 6-33 read/write 6-21 transfer control 6-26 SCSI interrupt enable one register 5-55 SCSI interrupt enable zero register 5-53 SCSI interrupt pending bit 5-33 SCSI interrupt status one register 5-59 SCSI interrupt status zero register 5-56 SCSI isolation mode bits 5-72 SCSI longitudinal parity register 5-60 SCSI loopback mode bit 5-74 SCSI low level mode bit 5-74 SCSI MSG/ signal bit 5-28 SCSI output control latch register 5-21 SCSI output data latch register 5-78 SCSI parity error bit 5-55 SCSI phase mismatch bit 5-54 SCSI reset condition bit 5-55 SCSI RST/ received bit 5-58 SCSI RST/ signal bit 5-27 SCSI SCRIPTS operation 6-1 sample instruction 6-3 SCSI SDP0/ parity signal bit 5-27 SCSI SDP1 signal bit 5-30 SCSI selected as ID bits 5-70 SCSI selector ID register 5-22 SCSI status one register 5-27 SCSI status two register 5-29 SCSI status zero register 5-26 SCSI synchronous offset maximum 5-71 SCSI synchronous offset zero bit 5-71 SCSI test one register 5-72 SCSI test three register 5-75 SCSI test two register 5-73 SCSI test zero register 5-70 SCSI timer one register 5-66 SCSI timer zero register 5-64 SCSI timing diagrams 7-51 SCSI transfer register 5-15 SCSI true end of process bit 5-36 SCSI valid bit 5-22 SCSI wide residue register 5-61 SDID register 5-18
IX-6
Index
select with SATN/ on a start sequence bit 5-4 selected bit 5-54, 5-57 selection or reselection time-out bit 5-56, 5-59 selection response logic test bits 5-71 semaphore bit 5-32 SFBR register 5-20 shadow register test mode bit 5-40 SI_O/ status bit 5-23 SIDL least significant byte full bit 5-26 SIDL most significant byte full bit 5-29 SIDL register 5-77 SIEN0 register 5-53 SIEN1 register 5-55 SIGP bit 5-32, 5-36 single step interrupt bit 5-24, 5-50 single step mode bit 5-51 single-ended operation 2-19 SIST0 register 5-56 SIST1 register 5-59 SLPAR high byte enable 5-10 SLPAR mode bit 5-10 SLPAR register 5-60 SMSG/ status bit 5-23 SOCL least significant byte full bit 5-26 SOCL register 5-21 SODL most significant byte full bit 5-29 SODL register 5-78 SODR least significant byte full bit 5-26 SODR most significant byte full bit 5-29 software reset bit 5-32 source I/O memory enable bit 5-48 SREQ/ status bit 5-22 SSEL/ status bit 5-22 SSID register 5-22 SSTAT0 register 5-26 SSTAT1 register 5-27 SSTAT2 register 5-29 stacked interrupts 2-32 start DMA operation bit 5-52 start SCSI transfer 5-8 start sequence bits 5-4 STEST0 register 5-70 STEST1 register 5-72 STEST2 register 5-73 STEST3 register 5-75 STIME0 register 5-64 STIME1 register 5-66 storage device management system (SDMS) 2-3 SWIDE register 5-61 SXFER register 5-15 synchronous clock conversion factor bits 5-12 synchronous data transfer rates 2-26 synchronous transfer period bits 5-15
TolerANT technology 1-5 benefits 1-5 extend SREQ/SACK filtering bit 5-74 TolerANT enable bit 5-75 totem pole output 4-6 transfer control instructions 6-26 and SCRIPTS instruction prefetching 2-6 transfer rate 1-6 synchronous 2-26
U
Ultra Ultra enable bit 5-12 Ultra SCSI benefits 1-4 designing an Ultra SCSI system 2-4 synchronous transfer period bits 5-15 unexpected disconnect bit 5-55, 5-58
W
WATN/ bit 5-4 wide SCSI always wide SCSI bit 5-74 chained block moves 2-34 chained mode bit 5-9 enable wide SCSI bit 5-12 SWIDE register 5-61 wide SCSI receive bit 5-11 wide SCSI send bit 5-10 wide SCSI receive bit 5-11 wide SCSI send bit 5-10 won arbitration bit 5-27 write and invalidate enable bit 5-38
T
target mode bit 5-6 TEMP register 5-38 temporary register 5-38 termination 2-23 timer test mode bit 5-76 timings PCI 7-50 SCSI 7-51 TolerANT 7-7 TolerANT enable bit 5-75
Index
IX-7
IX-8
Index
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